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minirisc ? LR4500 superscalar microprocessor order number c14043 technical manual
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. document db14-000066-00, first edition (may 1998) this document describes revision a of lsi logic corporations minirisc ? LR4500 superscalar microprocessor and will remain the of?cial reference source for all revisions of this product until rescinded by an update. to receive product literature, call us at 1.800.574.4286 (u.s. and canada); +32.11.300.531 (europe); 408.433.7700 (outside u.s., canada, and europe) and ask for department jds; or visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or lia- bility arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1997, 1998 by lsi logic corporation. all rights reserved. trademark acknowledgment lsi logic logo design, coreware, g10, and minirisc are registered trademarks and serialice is a trademark of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
contents iii contents preface chapter 1 introduction 1.1 LR4500 overview 1-1 1.2 LR4500 features 1-3 chapter 2 functional blocks 2.1 cw4011 shell 2-2 2.1.1 cw4011 core 2-3 2.1.2 multiply/divide unit 2-3 2.1.3 memory management unit shell 2-3 2.1.4 write back buffer 2-3 2.1.5 caches 2-4 2.2 synchronous dram controller 2-4 2.3 scbus to local i/o bus converter 2-4 2.4 pll clock circuit 2-5 2.5 iceport uart 2-6 2.6 pipeline architecture 2-7 chapter 3 programming model 3.1 register set 3-2 3.2 memory mapping 3-4 3.3 system con?guration 3-5 3.3.1 ccc register 3-5 3.3.2 lbus controller registers 3-9
iv contents chapter 4 instruction set 4.1 instruction set 4-1 4.2 cw4011 instruction set extensions 4-15 4.3 cpu instruction opcode bit encoding 4-30 chapter 5 bus interface descriptions 5.1 external interfaces 5-2 5.1.1 mbus interface 5-2 5.1.2 lbus interface 5-5 5.1.3 phase-locked loop (pll) clock signals 5-9 5.1.4 test signals 5-10 5.1.5 cw4011 core monitor signal 5-11 5.2 internal interface 5-11 5.2.1 scbus interface 5-11 5.2.2 external buffering for scbus signals 5-19 5.2.3 cw4011 shell reset/interrupt interface 5-22 chapter 6 dram controller and memory bus 6.1 dram types and available dram address area 6-1 6.2 memory interface 6-2 6.3 address bit assignment 6-4 6.4 dram controller con?guration register 6-5 6.5 dram mode register 6-9 6.6 dram refresh 6-11 6.7 dram commands 6-13 6.8 initializing dram and programming the mode register 6-14 6.9 dram transactions 6-19 chapter 7 scbus and local i/o bus converter module 7.1 lbus features 7-1 7.2 LR4500 as master on the lbus 7-2 7.3 LR4500 as slave on the lbus 7-5 7.4 scbus timeout watchdog timer 7-8 7.5 external vectored interrupt (evint) support 7-9
contents v chapter 8 cache con?guration and maintenance 8.1 cache con?guration 8-1 8.2 cache maintenance 8-4 chapter 9 iceport 9.1 overview 9-1 9.2 iceport features 9-2 9.3 iceport functional blocks 9-3 9.3.1 receive and transmit interface logic 9-4 9.3.2 generic interface logic 9-4 9.3.3 scbus interface logic 9-4 9.4 iceport signals 9-5 9.4.1 monitored scbus signals 9-6 9.4.2 other scbus signals 9-7 9.4.3 iceport scan and clocking i/o signals 9-8 9.5 iceport registers 9-9 9.5.1 rx status register 9-11 9.5.2 rx setup register 9-12 9.5.3 rx data register 9-12 9.5.4 tx status register 9-13 9.5.5 tx data register 9-14 9.6 iceport operations 9-14 9.6.1 scbus read/write transactions 9-14 9.6.2 reset 9-17 9.6.3 the serial bit stream 9-18 9.6.4 iceport receive and transmit 9-18 9.6.5 clock domains and properties 9-21 9.7 iceport pin buffers and drivers 9-22 chapter 10 organization of clock and exception signals 10.1 clock circuitry 10-1 10.2 exception inputs 10-3 chapter 11 speci?cations 11.1 electrical characteristics 11-1 11.1.1 absolute maximum ratings 11-1
vi contents 11.1.2 recommended operating conditions 11-2 11.1.3 input/output capacitance 11-2 11.1.4 dc characteristics 11-2 11.1.5 ac timing speci?cations 11-3 11.2 packaging 11-6 11.3 pinouts 11-8 customer feedback figures 1.1 block diagram of LR4500 and evaluation board circuitry 1-2 2.1 LR4500 block diagram 2-2 2.2 LR4500 pll circuit diagram 2-6 2.3 LR4500 instruction pipeline 2-7 3.1 LR4500 master/slave memory map 3-4 3.2 ccc register 3-5 3.3 scbus status register 3-10 3.4 scbus error address register 3-10 3.5 external vectored interrupt register 3-11 5.1 LR4500 interfaces 5-2 5.2 mbus interface 5-3 5.3 lbus interface 5-6 5.4 scbus interface 5-13 5.5 buffering for scap[31:0] address bus 5-20 5.6 buffering for scdp[63:0] data bus 5-21 5.7 buffering for scben[7:0] byte enable 5-21 5.8 shell reset/interrupt interface 5-22 6.1 LR4500 interface with dram 6-3 6.2 scbus dram address bit assignment 6-4 6.3 dram controller con?guration register format 6-5 6.4 dram mode register format 6-10 6.5 dram refresh interval timer 6-12 6.6 timing requirements for dram initialization sequence 6-18 6.7 single burst read transaction 6-20 6.8 two continuous single write transactions 6-21 6.9 burst write transaction 6-22 7.1 timing requirements for an scbus-to-lbus read
contents vii transaction 7-3 7.2 timing requirements for an scbus-to-lbus write transaction 7-4 7.3 timing requirements for lbus-to-scbus read transaction 7-6 7.4 timing requirements for lbus-to-scbus write transaction 7-7 7.5 scbus error address and error status register bit format 7-8 7.6 external vectored interrupt register bit format 7-9 9.1 cw4011 design with iceport 9-2 9.2 iceport block diagram 9-3 9.3 rx status register 9-11 9.4 rx setup register 9-12 9.5 rx data register 9-13 9.6 tx status register 9-13 9.7 tx data register 9-14 9.8 read transaction 9-16 9.9 write transaction 9-16 9.10 serial bit stream 9-18 9.11 rx and tx blocks 9-19 9.12 received bit timing 9-20 10.1 LR4500 pll clock circuitry 10-2 10.2 timing requirements for the cw4011 and lbus clocks 10-3 10.3 exception inputs synchronization circuitry 10-4 10.4 timing requirements for synchronization circuit 10-4 11.1 ac timing for LR4500 inputs and outputs 11-5 11.2 256 pqfpt mechanical drawing 11-6 11.3 256 pqfpt pinouts 11-8 tables 3.1 LR4500 registers 3-2 4.1 load and store instructions 4-2 4.2 load linked mips ii instructions 4-3 4.3 alu immediate instructions 4-4 4.4 alu three-operand register type instructions 4-5 4.5 shift instructions 4-6 4.6 multiply/divide instructions 4-7 4.7 extended computational instructions 4-8 4.8 jump instructions 4-9
viii contents 4.9 branch instructions 4-10 4.10 branch likely instructions 4-11 4.11 trap instructions 4-12 4.12 special instructions 4-13 4.13 cp0 instructions 4-13 4.14 cache maintenance instructions 4-14 4.15 cw4011 opcode bit encoding 4-31 4.16 special opcode bit encoding 4-32 4.17 regimm opcode rt bit encoding 4-32 4.18 cache x2 opcode rt bit encoding 4-33 4.19 copz rs opcode bit encoding 4-33 4.20 copz rt opcode bit encoding 4-33 4.21 cp0 opcode bit encoding 4-34 6.1 dram con?gurations 6-2 6.2 scbus address and mbus address bit assignment 6-5 6.3 relationship between frequency and latency 6-9 6.4 refresh register programming values 6-13 6.5 refresh register setting for 80 mhz 12.5 ns dram 6-13 6.6 summary of dram commands and mbus control signals 6-14 6.7 timing signals 6-16 8.1 cache size and accessing 8-2 8.2 d-cache scratchpad ram con?guration 8-3 8.3 i-cache instruction ram con?guration 8-3 9.1 iceport signals 9-6 9.2 iceport register addresses 9-10 10.1 summary of LR4500 clocks 10-2 11.1 absolute maximum ratings 11-1 11.2 recommended operating conditions 11-2 11.3 input/output capacitance 11-2 11.4 dc characteristics 11-3 11.5 LR4500 ac timing speci?cations 11-4
preface ix preface this book is the primary reference and technical manual for the minirisc ? LR4500 superscalar microprocessor reference device. the book contains a complete functional description of the LR4500, with physical and electrical speci?cations. audience this book assumes that you are familiar with microprocessors and related support devices. the book targets: engineers and managers who are evaluating the LR4500 for possible use in system design engineers who are designing the LR4500 into a system organization this book has the following chapters: chapter 1, introduction, provides an overview of the reference device, de?nes the devices context on an evaluation board, and lists the devices features. chapter 2, functional blocks , provides information about all functional blocks that are part of the LR4500: the cw4011 shell, the synchronous dram controller (dramc), the scbus/lbus controller (sclc), the pll clock circuit, and the iceport uart. the chapter also describes the LR4500 pipeline architecture. chapter 3, programming model , provides information about the LR4500 programming model, including a list of LR4500 registers, information about memory mapping, and descriptions of the LR4500 registers used to con?gure the system.
x preface chapter 4, instruction set , lists and describes the instructions that make up the LR4500 instruction set, de?nes the instruction set extensions, and describes cpu instruction opcode bit encoding. chapter 5, bus interface descriptions , describes the interface signals for the major LR4500 interfaces including the signals that provide the external interface between the LR4500 and external devices, and the interface signals internal to the LR4500. the chapter also describes the buffering required for certain interface signals. chapter 6, dram controller and memory bus , describes the synchronous dram controller and the memory bus. it also provides timing information for different dram transactions. chapter 7, scbus and local i/o bus converter module , describes the lbus and explains how the LR4500 interacts with the lbus through the sclc module. chapter 8, cache con?guration and maintenance , describes the i-cache and d-cache con?gurations and explains how to maintain the caches after power is turned on. chapter 9, iceport , describes the iceport building block that provides a full-duplex serial uart (universal asynchronous receive and transmit) port for the LR4500. chapter 10, organization of clock and exception signals , describes the organization of the LR4500 clock signals and the exception-handling signals. chapter 11, speci?cations , de?nes the electrical characteristics of the LR4500. it also provides packaging information, including the mechanical layout of the LR4500, the chips dimensions, and pin locations.
preface xi related publications minirisc cw4011 superscalar microprocessor core technical manual , order number c14040 minirisc bdmr4011 evaluation board users guide, order number c14052. conventions used in this manual assert means to drive a signal true or active; deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x, for example, 0x32cf. the following notational conventions are used throughout this manual. notation example meaning and use courier typeface .nwk ?le names of commands, ?les, symbols, parts, directories, modules, and macrocells are shown in courier typeface. bold typeface fd1sp in a command line, keywords are shown in bold, nonitalic typeface. enter them exactly as shown.
xii preface
1-1 chapter 1 introduction this chapter provides an overview and de?nes the features of the minirisc LR4500 superscalar microprocessor reference device. 1.1 LR4500 overview the LR4500 is a chip implementation of the minirisc cw4011 microprocessor core and shell. it is the second lsi logic implementation of a 32-bit mips ii compatible, superscalar cpu. as shown in figure 1.1 , the LR4500 contains the following circuitry, housed on an evaluation board: the maximum con?guration cw4011 shell, which is an unencrypted verilog model that contains C cw4011 core C multiply/divide unit (mdu) C instruction cache (i-cache) C data cache (d-cache) C memory management unit (mmu) without translation look-aside buffer (tlb) C write back buffer (wb). you can con?gure certain modules in the shell by programming the con?guration register in cw4011 coprocessor 0 (cp0). for example, you can turn off the mdu and the wb. depending on the application, the LR4500 generally uses all modules.
1-2 introduction the dram controller that provides the memory bus (mbus) interface between the LR4500 and external synchronous memory devices. the scbus/lbus converter that controls the local i/o bus (lbus) and external lbus devices a phase-locked loop (pll) circuit that supplies clock inputs to the other modules in the LR4500 the iceport uart (universal asynchronous receiver/transmitter) is used to download serialice? application software and to debug the LR4500. figure 1.1 block diagram of LR4500 and evaluation board circuitry chapter 2, functional blocks , provides detailed information about the functional elements of the LR4500. the LR4500 is housed on an evaluation board (bdLR4500) that allows you to use and test the LR4500. in addition to the LR4500, the board contains: the dram array that communicates with the LR4500 through the mbus. scbus cache invalidation interface interface local io bus memory bus (lbus) (mbus) synchronous controller (sdramc) dram scbus/lbus converter (sclc) synchronous main memory dram boot serial ethernet controller (sonic) rom i/o phase-locked LR4500 loop (pll) cell iceport (uart) cw4011 shell reference device evaluation board microprocessor
LR4500 features 1-3 the lbus that allows you to plug in devices such as a boot-rom, serial i/o devices, and an external ethernet controller. (the lbus is a simple, generic interface for peripheral devices such as roms, rams, uarts. it has a demultiplexed 32-bit address bus and 32-bit data bus, and it is similar to the 486 vlbus.) 1.2 LR4500 features the LR4500 microprocessor has the following features: system clock operating at up to 100 mhz, with 150 dhrystone mips performance superscalar microprocessor support for the mips ii 32-bit instruction set: C up to two instructions executed per clock cycle C four-deep write buffer C load scheduling C r3000/r4000 compatible mode for the exception return and status register 32-bit timer (r4000 compatible) scbus watchdog timer with error reporting features full internal scan testing serialice debugging support provided through the iceport uart interface scbus/lbus converter to control the lbus and external lbus devices easily implemented interface to the sonic ethernet controller synchronous dram controller, with 64-bit wide data transfer, interfaces to the following 16-mbit sdrams (synchronous drams): C 1-m x 16-bit sdram devices in an 8-mbyte or 16-mbyte con?guration C 2-m x 8-bit sdram devices in a 16-mbyte or 32-mbyte con?guration C 4-m x 4-bit sdram devices in a 32-mbyte or 64-mbyte con?guration
1-4 introduction pll circuit for internal system clock; synchronizes internal system clock with an external clock 3.3 v operation LR4500 power - 4.19 ma (at 3.46 v and 100 mhz) packaged in a 256-pin pqfpt (plastic quad flat package) cache con?guration: C direct-mapped or two-way set-associative i-cache and d-cache C 1-kbyte, 2-kbyte, 4-kbyte, or 8-kbyte cache sets, organized as either direct-mapped (single set) cache with maximum cache size of 8 kbytes, or as a two-way set-associative cache with a maximum cache size of 16 kbytes. simpli?ed kseg0 and kseg1 memory management unit without tlb fast multiplier supporting multiply-accumulate operations high-performance multiplier delivers three-cycle latency and one cycle throughput for mac (multiply with accumulate) instructions support for both big-endian and little-endian formats
2-1 chapter 2 functional blocks this chapter describes each of the LR4500 functional blocks and the LR4500 pipeline architecture. the chapter is divided into the following sections: cw4011 shell , o n page 2-2 . synchronous dram controller , o n page 2-4 . scbus to local i/o bus converter , o n page 2-4 . pll clock circuit , o n page 2-5 . iceport uart , o n page 2-6 . pipeline architecture , o n page 2-7 .
2-2 functional blocks figure 2.1 LR4500 block diagram 2.1 cw4011 shell the cw4011 shell consists of the cw4011 core, the mdu (multiply/divide unit), the mmu (memory management unit), the wb (write back buffer), the i-cache (instruction cache), and the d-cache (data cache). with the exception of the cw4011 core, you can turn off certain modules in the cw4011 shell, for example the mdu or the wb, to ?t your own asic design. scbus cw4011 core interface multiply/ divide alu simple write back buffer d-cache set-0 d-cache set-1 cp0 isu lsu biu unit i-cache set-0 i-cache set-1 mmu (no tlb) local io bus memory bus (lbus) (mbus) synchronous controller (sdramc) dram scbus/lbus converter (sclc) LR4500 microprocessor reference device phase-locked loop (pll) cell iceport (uart) cw4011 shell system clock cache invalidation interface
cw4011 shell 2-3 2.1.1 cw4011 core the cw4011 core is an encrypted verilog rtl model that is part of lsi logics coreware? library. the cw4011 core is a prede?ned hardmacro that contains the following basic microprocessor elements: instruction scheduling unit (isu) load/store unit (lsu) arithmetic logic unit (alu) coprocessor 0 (cp0) bus interface unit (biu) the cw4011 core executes all mips ii 32-bit based instructions except for multiply/divide instructions. these instructions are handled by the mdu, which is part of the cw4011 shell. for detailed information about the cw4011 core, refer to the minirisc cw4011 superscalar microprocessor technical manual . 2.1.2 multiply/divide unit the multiply/divide unit supports multiply-add/subtract operations as well as multiply and divide. the multiply instruction executes in three cycles. the multiply-add/subtract instruction is optimized to one cycle. 2.1.3 memory management unit shell the mmu does not have a tlb. kseg0 and kseg1 are mapped to the ?rst 512 mbyte space, which is the bottom of the memory space. the kuseg and kseg2 blocks are directly mapped to the physical address space without any change. section 3.2, on page 3-4 , provides more information on this subject. 2.1.4 write back buffer the cw4011 core uses this buffer when the d-cache operates in write back mode. when a cache miss occurs and the victim entry contains a dirty line, the dirty data is written into the write back buffer instead of the main memory. this reduces the latency of the cache re?ll for missed addresses. data in the write back buffer is written into the main memory after the re?ll is completed.
2-4 functional blocks 2.1.5 caches the LR4500 has separate instruction and data cachesi-cache and d-cachethat can be organized as direct-mapped or two-way set- associative caches. the cache controllers support con?gurations of 1, 2, 4, or 8 kbytes for each set. thus, the smallest supported con?guration is a 1-kbyte direct-mapped cache, and the largest is a 16-kbyte two-way set-associative cache, with 8 kbytes per set. you can select between write back and write through modes. you can also con?gure both sets of the d-cache and one set of the i-cache for scratchpad ram mode. refer to chapter 8 , cache con?guration and maintenance , for more information on this subject. 2.2 synchronous dram controller the dram controller is part of the LR4500 reference device, and it is external to the cw4011 shell, as shown in figure 2.1 on page 2-2 .it generates dram transactions in response to requests from the cw4011 core or from the sclc module. the dram controller also generates initialization cycles and refresh cycles for dram. chapter 6 , dram controller and memory bus , provides detailed information about dram and the dram controller. 2.3 scbus to local i/o bus converter the sclc module provides an interface between the internal cw4011 microprocessor bus (scbus) and the external local i/o bus (lbus). the lbus connects such devices as boot-rom, serial i/o devices, and the ethernet controller to the LR4500. the scbus is a 32-bit address, 64-bit data bus. the lbus, which is a subset of the industrial standard vlbus, is a 32-bit address, 32-bit data bus. the cw4011 uses the sclc module to access devices on the lbus. devices on the lbus access the dram main memory through the sclc module and the dram controller. the cw4011 microprocessor generally has ownership of the scbus and the lbus. when a device on the lbus wants to access the dram, it asserts the bus hold request signal on the lbus. the sclc module
pll clock circuit 2-5 detects the asserted signal and then asserts the bus hold request to the cw4011. the cw4011 asserts the grant signal to the sclc module, and the sclc module then asserts the hold acknowledge signal to the lbus device. 'scbus and local i/o bus converter module" provides detailed information about the lbus. 2.4 pll clock circuit the pll circuit is an lsi logic pll cell ( pllpgmcb ) part that drives the clock signals to the cw4011 shell and the other modules that are part of the LR4500. the system clock, sclkp, drives the pllrefp input. figure 2.1 on page 2-2 shows the relationship between the pll circuit and the other LR4500 modules. figure 2.2 shows the layout of the LR4500 pll circuit. when using the pll circuit, you must observe the following design requirements: provide capacitance devices. provide a resistor between plllp2p and pllagnd. connect other pll circuit inputs to v dd or gnd. leave pllctop outputs open. for more information about the pll circuit, refer to the lsi logic g10 ? -p cell-based asic products design manual and g10-p cell-based asic products databook .
2-6 functional blocks figure 2.2 LR4500 pll circuit diagram 2.5 iceport uart the iceport is a full-duplex serial uart port. it is used for downloading application software and debugging the LR4500. the iceport works with an ice controller at baud rates up to 1 mbaud, and it is integrated with the sclc and dram controller modules on the scbus. 'iceport' 'iceport' provides detailed information about the iceport uart. pllenp pllrefp pllvdd pllvss plliddtp plltdp plltstp az (&ibuf) az (&ddrv..no pi & po) az (pllvdd..no pi & po) az (pllvss..no pi & po) az (&iiddtn) pllvss az (&ibuf) az (&ibuf) az (&ibuf) pllctrn 11-bit iddtn a s z (mux21hp) plllp2p pllagnd az (&ddrv..no pi & po) c r c1 io a en (plllp2..io is de?ned as both in and out) a z a z sclkp nbsclkp pllvdd fb ref lp2 ckout ckoutp xlp2p xpllrefp xpllvdd xpllvss xplliddtn xplltdp xplltstp xpllctrn pllctop az (&b1) xpllctop xpllenn xpllagnd...alias (pllpgmcb) cp cd ctop (20 pf) (0.001 uf) (200 ohm) (active high) b (bufa) 0 2:1 multiplexer counter xscanmonp
pipeline architecture 2-7 2.6 pipeline architecture the LR4500 has two identical concurrent ?ve-stage pipelines that are part of the cw4011 core. these pipelines provide the LR4500 with its superscalar capabilities. as shown in figure 2.3 , there is an even pipeline and an odd pipeline. each of the ?ve pipeline stages can be viewed as a pair of instruction slots (one slot for each pipeline.) so an instruction in the even pipeline at the ex stage may be referred to as the even slot of the ex stage. in addition to the ?ve basic pipeline stages, each pipeline also has a conditional queuing stage (q). figure 2.3 LR4500 instruction pipeline the ?rst two pipeline stages and the queuing stage are used during instruction fetch, and the last three stages are used during instruction execution. once a stage has accepted an instruction from the previous stage it must hold the instruction for re-execution in case the pipeline stalls. the pipeline stages perform the following functions: if (instruction fetch). the LR4500 fetches the instruction during the ?rst stage. q (queuing). this conditional queueing stage boosts branch instructions. depending on the branches and register con?icts, instructions may either enter this stage or be advanced straight to the rd stage. ex cr rd q if instruction fetch instruction execution wb ex cr rd q if wb even slot, odd slot, pipeline 0 pipeline 1 1. branch instruction encountered. 2. q state bypassed.
2-8 functional blocks rd (read). during this stage, any required operands are read from the register file while the instruction is being decoded. ex (execution). this stage performs a number of functions: all instructions are executed, conditional branches are resolved, the address calculation for load and store instructions is performed. cr (cache read). this stage is used to access the cache for load and store instructions. data is returned to the register bypass logic at the end of this stage. wb (write back). results are written into the register file during this stage. for a more detailed description of the cw4011 pipeline, refer to the minirisc superscalar microprocessor core technical manual .
3-1 chapter 3 programming model this chapter provides information about the LR4500 microprocessor programming model. the term programming model refers to the way in which data is arranged in registers and in memory. the chapter provides a list of LR4500 registers on page 3-2 describes LR4500 memory mapping on page 3-4 describes how to con?gure the system using LR4500 registers on page 3-5 in addition, the following sections in other chapters of this manual provide supplementary information related to the programming model: dram controller and memory bus on page 6-1 scbus timeout watchdog timer on page 7-8 cache con?guration and maintenance on page 8-1 the minirisc cw4011 superscalar microprocessor core technical manual describes the memory management unit and coprocessor 0 (cp0).
3-2 programming model 3.1 register set table 3.1 lists the LR4500 registers and provides the physical and virtual addresses, and the register numbers. the registers are listed in functional blocks and arranged alphabetically within each functional block. table 3.1 LR4500 registers register name physical address virtual address number cp0 exception processing registers badvaddr (bad virtual address) physical and virtual addresses are not applicable to cp0 exception processing registers. 8 bda (breakpoint data address) 19 bdam (breakpoint data address mask) 21 bpc (breakpoint program counter) 18 bpcm (breakpoint pc mask) 20 cause 13 ccc (con?guration and cache control) 1 16 compare 11 count 9 dcs (debug control status) 7 epc (exception program counter) 14 errorpc 30 lladr (load linked address) 17 prid (processor revision identi?er) 15 status 12
register set 3-3 lbus controller registers external vectored interrupt 2 0x 1010 0008 0x b010 0008 n/a scbus error address 3 0x 1010 0000 0x b010 0000 n/a scbus error status 4 0x 1010 0004 0x b010 0004 n/a dram controller registers dram refresh register 5 0x 1000 0004 0x b000 0004 n/a dram controller con?guration 6 0x 1000 0000 0x b000 0000 n/a iceport registers rx status 7 0x10ff 0000 8 0xb0ff 0000 8 n/a rx setup 7 0x10ff 0000 8 0xb0ff 0000 8 n/a rx data 0x10ff 0004 0xb0ff 0004 n/a tx status 0x10ff 0008 0xb0ff 0008 n/a tx data 0x10ff 000c 0xb0ff 000c n/a 1. see ccc register on page 3-5 2. see external vectored interrupt register on page 3-11 3. see scbus error address register on page 3-10 4. see scbus error status register on page 3-10 5. see dram refresh on page 6-12 6. see dram controller con?guration register on page 6-5 7. see iceport registers on page 9-9 all other registers listed in this table are described in the minirisc cw4011 superscalar microprocessor core technical manual 8. the physical address for the rx status register is the same as the physical address for the rx setup register. similarly, the virtual addresses are the same. the rx status register is a read register and the rx setup register is a write register. this means that when the addresses are accessed, the register accessed depends on the condition of the read/write signal. table 3.1 LR4500 registers (cont.) register name physical address virtual address number
3-4 programming model 3.2 memory mapping figure 3.1 shows the physical memory map of the LR4500 reference device, where the LR4500 is master of the lbus and an lbus device is slave, and the physical memory map where an lbus device is the lbus master and the LR4500 is slave. in both cases, address spaces are linear 4-gbyte spaces. lbus master devices cannot access LR4500 internal memory-mapped registers. synchronous dram main memory that is interfaced to the LR4500 is located at address space 0x0000 0000 through 0x03ff ffff. the LR4500 works as an lbus slave device for this 64-mbyte memory space. there is no guarantee that memory devices exist in the entire 64-mbyte area. software, in the form of a setup/bootstrap utility or equivalent must check installed memory size when the system is initialized. the upper 192-mbyte space is reserved as an extended main memory area. LR4500 internal registers for dram controller and error reporting are located in the internal registers area between addresses 0x1000 0000 and 0x10ff ffff. these registers must be accessed through kseg1 , the uncached unmapped area. the virtual address for these registers is 0xb000 0000 through 0xb0ff ffff. figure 3.1 LR4500 master/slave memory map 0x0000 0000 0x0400 0000 0x1000 0000 0xffff ffff lbus access area internal register area LR4500 master address map 0x1100 0000 LR4500 slave address map 0x0000 0000 0x0400 0000 0x1000 0000 0xffff ffff lbus access area unusable area 0x1100 0000 lowest order address highest order address reserved main memory area reserved main memory area dram main memory area dram main memory area
system con?guration 3-5 3.3 system con?guration LR4500 has a number of features that allow you to modify the system con?guration. this section describes the con?guration and cache control (ccc) register, which is part of the cw4011 core, and several lbus registers, which are part of the sclc module. you can also con?gure the dram, as described in chapter 6 , dram controller and memory bus . 3.3.1 ccc register the con?guration and cache control (ccc) register is part of cp0, the system coprocessor. the ccc register allows you to use software to con?gure various pieces of the core design, such as the bus interface unit (biu) and the controllers for the i-cache and d-cache. you can read from the ccc register using the mfc0 instruction, and write to it using the mtc0 instruction. table 4.14 on page 4-14 describes these instructions. the registers address in cp0 is 16. figure 3.2 shows the bit con?guration of the ccc register. all bits are initialized to 0 at reset, so that the caches are not available until the register is programmed. figure 3.2 ccc register r reserved [31:29] this ?eld is reserved. the bits are cleared to 0. ewp external write priority 28 this bit de?nes the arbitration priority on the scbus between a data read and data write transaction in the 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ewp sdb ir1 evi cmp iie die mul mad tmr bge ie0 ie1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 is[1:0] de0 de1 ds[1:0] ipwe ipws[1:0] te wb sr0 sr1 isc tag inv
3-6 programming model 4-deep write buffer. clearing the bit to 0 gives a higher priority to a data read request if the read address does not match the write address in the write buffer. setting the bit to 1 gives higher priority to data write transactions. sdb scan debug 27 this bit is reserved. it must be set to 0. ir1 i-cache scratchpad ram 26 setting this bit to 1 enables scratchpad ram mode in set-1 of the i-cache. clearing it to 0 disables scratchpad ram mode. evi external vectored interrupt 25 this bit enables and disables external vectored interrupt. setting the bit to 1 enables the interrupt and clearing it to 0 disables the interrupt. cmp r3000 compatibility 24 this bit enables and disables r3000 compatibility mode. setting the bit to 1 enables the mode and clearing it to 0 disables the mode. iie i-cache invalidate enable 23 this bit enables and disables the i-cache invalidate request. setting the bit to 1 enables the request and clearing it to 0 disables the request. die d-cache invalidate enable 22 this bit enables and disables the d-cache invalidate request. setting the bit to 1 enables the request and clearing the bit to 0 disables the request. mul multiplier 21 this bit enables and disables the hardware multiplier. setting the bit to 1 enables the multiplier and clearing the bit to 0 disables the multiplier. mad multiply accumulate 20 this bit allows the multiplier to support accumulate extensions. setting the bit to 1 enables the feature and clearing the bit disables the feature. when this bit is set, mul must also be set.
system con?guration 3-7 tmr timer 19 setting this bit to 1 enables the timer facility associated with the cw4011 cores count and compare registers. when this bit is set, and the value of the count register equals the value of the compare register, interrupt bit ip7 in the cause register is set. ip7 causes an interrupt in the next execution cycle, provided that interrupts are enabled by setting the interrupt enable bit in the status register to 1 and clearing the error level and exception level bits in the status register to 0. bge biu bus grant enable 18 this bit enables and disables the biu bus grant. setting this bit to 1 enables the external bus master. clearing it to 0 causes the cw4011 core to ignore the external bus master. ie0 i-cache set-0 enable 17 this bit enables and disables set-0 of the i-cache. setting the bit to 1 enables set-0 and clearing the bit to 0 disables set-0. ie1 i-cache set-1 enable 16 this bit enables and disables set-1 of the i-cache. setting the bit to 1 enables set-1 and clearing the bit to 0 disables set-1. is[1:0] i-cache size [15:14] the is[1:0] ?eld determines the size of each i-cache set. the ?eld settings are de?ned as follows: de0 d-cache set-0 enable 13 this bit enables and disables set-0 of the d-cache. setting the bit to 1 enables set-0 and clearing the bit to 0 disables set-0. is1 is0 cache set size 0 0 1 kbyte 0 1 2 kbyte 1 0 4 kbyte 1 1 8 kbyte
3-8 programming model de1 d-cache set-1 enable 12 this bit enables and disables set-1 of the d-cache. setting the bit to 1 enables set-1 and clearing it to 0 disables set-1. ds[1:0] d-cache size [15:14] the ds[1:0] ?eld determines the size of each d-cache set. the ?eld settings are de?ned as follows: ipwe in-page write enable 9 this bit enables and disables in-page write operations. setting the bit to 1 enables in-page write and clearing it to 0 disables in-page write. ipws[1:0] in-page write size [8:7] the ipws[1:0] ?eld determines the size of the i-cache set. the ?eld settings are de?ned as follows: te tlb enable 6 this bit enables and disables the tlb. since the LR4500 does not support a full tlb, this bit has no effect. wb write back 5 this bit de?nes the caching algorithm, for kseg0 . it also de?nes the caching algorithm for kuseg and kseg2 if there is no tlb or if the tlb is disabled. setting the bit to 1 enables a write back operation and clearing the bit to 0 enables a write through operation. ds1 ds0 cache set size 0 0 1 kbyte 0 1 2 kbyte 1 0 4 kbyte 1 1 8 kbyte ipws1 ipws0 in-page write size 0 0 1 kbyte 0 1 2 kbyte 1 0 4 kbyte 1 1 8 kbyte
system con?guration 3-9 sr0 scratchpad ram mode set-0 4 this bit enables and disables scratchpad ram mode for set-0 of the d-cache. setting the bit to 1 enables scratchpad mode and clearing it to 0 disables scratchpad mode. sr1 scratchpad ram mode set-1 3 this bit enables and disables scratchpad ram mode for set-1 of the d-cache. setting the bit to 1 enables scratchpad mode and clearing it to 0 disables scratchpad mode. isc isolate cache 2 this bit enables isolate cache mode. this means that stores to the cache are not propagated to external memory. setting the bit to 1 enables the mode and clearing the bit to 0 disables the mode. tag tag test mode 1 this bit enables and disables tag test mode, which is used for cache maintenance. setting the bit to 1 enables the mode, which means that load and store operations access the tag rams and sample the tag bits tag data, hit, write back (d-cache only), and valid. clearing the bit to 0 disables tag test mode. this bit is used when isc=1. inv invalidate cache mode 0 this bit enables and disables invalidate cache mode, which is used for cache maintenance. setting the bit to 1 enables the mode. clearing the bit to 0 disables invalidate cache mode. this bit is used with isc = 1. 3.3.2 lbus controller registers the lbus controller has three 32-bit registers that store information about scbus errors and interrupts. they are the scbus error status register, the scbus error address register, and the external vectored interrupt register. you must access these registers through kseg1 . access to an unused address causes an scbus timeout error.
3-10 programming model 3.3.2.1 scbus error status register the scbus status register stores the bus error detect enable bit, bede, and the bus error detected bit, berr. the registers virtual address is 0xb010 0004 and its physical address is 0x1010 0004. for further information about this register, refer to scbus timeout watchdog timer on page 7-8 . figure 3.3 scbus status register reserved reserved [31:2] this ?eld is reserved. the bits are cleared to 0. bede bus error detect enable 1 when this bit is set to 1, the LR4500 is enabled to detect scbus errors. berr bus error 0 this bit is set to 1 when a bus error has been detected. 3.3.2.2 scbus error address register the scbus error address register stores the address of the transaction that has caused the bus error. the address remains stored during the period that the bus error bit, berr, is set. the registers virtual address is 0xb010 0000 and its physical address is 0x1010 0000. for further information about this register, refer to scbus timeout watchdog timer on page 7-8 . figure 3.4 scbus error address register 31 21 0 reserved (0) bede berr 31 0 error address[31:0]
system con?guration 3-11 3.3.2.3 external vectored interrupt register the external vectored interrupt register supports the LR4500 interrupt exception feature called external vectored interrupt. the registers virtual address is 0xb010 0008 and its physical address is 0x1010 0008. for further information about this register, refer to scbus timeout watchdog timer on page 7-8 . figure 3.5 external vectored interrupt register evia[31:2] external vectored interrupt address [31:2] this ?eld contains the exception vector address. hevi hardware external vectored interrupt 1 this bit is set when the error that caused the interrupt is a hardware error. sevi software external vectored interrupt 1 this bit is set when the error that caused the interrupt is a software error. 31 21 0 evia[31:2] hevi sevi
3-12 programming model
4-1 chapter 4 instruction set this chapter provides information about the LR4500 instruction set. it includes: a list of the LR4500 instructions and a de?nition of each instruction. de?nitions of the instruction set extensions. cpu instruction opcode bit encoding. 4.1 instruction set table 4.14 lists and describes the instructions that make up the LR4500 instruction set. the chip supports both mips i and 32-bit mips ii instructions and also implements additional extended instructions that are speci?c to the LR4500. the instructions are arranged alphabetically within the following functional groups: load and store instructions ,in table 4.1 on page 4-2 load linked mips ii instructions ,in table 4.2 on page 4-3 alu immediate instructions ,in table 4.3 on page 4-4 alu three-operand register type instructions ,in table 4.4 on page 4-5 shift instructions ,in table 4.5 on page 4-6 multiply/divide instructions ,in table 4.6 on page 4-7 extended computational instructions ,in table 4.7 on page 4-8 jump instructions ,in table 4.8 on page 4-9 branch instructions ,in table 4.9 on page 4-10
4-2 instruction set branch likely instructions ,in table 4.10 on page 4-11 trap instructions ,in table 4.11 on page 4-12 special instructions ,in table 4.12 on page 4-13 cp0 instructions ,in table 4.13 on page 4-13 cache maintenance instructions ,in table 4.14 on page 4-14 table 4.1 describes the load and store instructions. table 4.1 load and store instructions instruction format and description load byte lb rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. sign extend the contents of addressed byte and load into rt . load byte unsigned lbu rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. zero extend the contents of addressed byte and load into rt . load halfword lh rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. sign extend the contents of addressed halfword and load into rt . load halfword unsigned lhu rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. zero extend contents of addressed halfword and load into rt . load word lw rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address, and load the addressed word into rt . load word left lwl rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift addressed word left so that addressed byte is left most byte of a word. merge bytes from memory with contents of register rt and load result into register rt . load word right lwr rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift addressed word right so that addressed byte is right most byte of a word. merge bytes from memory with contents of register rt and load result into register rt .
instruction set 4-3 table 4.2 describes the load linked mips ii instructions. store byte sb rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. store least signi?cant byte of register rt at addressed location. store halfword sh rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. store least signi?cant halfword of register rt at addressed location. store word sw rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. store contents of register rt at addressed location. store word left swl rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift contents of register rt left so that the left most byte of the word is in the position of the addressed byte. store word containing shifted bytes into word at addressed byte. store word right swr rt, offset(base) sign extend the 16-bit offset and add to the contents of register base to form address. shift contents of register rt right so that the right most byte of the word is in the position of the addressed byte. store word containing shifted bytes into word at addressed byte. table 4.1 load and store instructions (cont.) instruction format and description table 4.2 load linked mips ii instructions instruction format and description load linked ll rt, offset(base) sign extend the 16-bit offset and add to the contents of the register base to form the address. load the addressed word into register rt . store conditional sc rt, offset(base) sign extend the 16-bit offset and add to the contents of the register base to form the address. conditionally store register rt at the address, based on whether the load-link has been broken. synchronize sync complete all outstanding load and store instructions before allowing any new load or store instruction to start.
4-4 instruction set table 4.3 describes the alu immediate instructions. table 4.3 alu immediate instructions instruction format and description add immediate addi rt, rs, immediate add 16-bit, sign extended immediate to register rs and place 32-bit result in register rt . trap on twos complement over?ow. add immediate unsigned addiu rt, rs, immediate add 16-bit, sign extended immediate to register rs and place 32-bit result in register rt . do not trap on over?ow. and immediate andi rt, rs, immediate zero extend 16-bit immediate , and with contents of register rs , and place result in register rt . exclusive or immediate xori rt, rs, immediate zero extend 16-bit immediate , exclusive or with contents of register rs , and place result in register rt . load upper immediate lui rt, immediate shift 16-bit immediate left 16 bits. set least-signi?cant 16 bits of word to zeros. store result in register rt . or immediate ori rt, rs, immediate zero extend 16-bit immediate , or with contents of register rs , and place result in register rt . set on less than immediate slti rt, rs, immediate compare 16-bit, sign extended immediate with register rs as signed 32-bit integers. result = 1 if rs is less than immediate; otherwise result = 0. place result in register rt . set on less than immediate unsigned sltiu rt, rs, immediate compare 16-bit, sign extended immediate with register rs as unsigned 32-bit integers. result = 1 if rs is less than immediate ; otherwise result = 0. place result in register rt .
instruction set 4-5 table 4.4 describes the alu three-operand register type instructions. table 4.4 alu three-operand register type instructions instruction format and description add add rd, rs, rt add contents of registers rs and rt and place 32-bit result in register rd . trap on twos complement over?ow. add unsigned addu rd, rs, rt add contents of registers rs and rt and place 32-bit result in register rd . do not trap on over?ow. and and rd, rs, rt bitwise and contents of registers rs and rt and place result in register rd . exclusive or xor rd, rs, rt bitwise exclusive or contents of registers rs and rt and place result in register rd . nor nor rd, rs, rt bitwise nor contents of registers rs and rt and place result in register rd . or or rd, rs, rt bitwise or contents of registers rs and rt and place result in register rd . set on less than slt rd, rs, rt compare contents of registers rt and rs (as signed, 32-bit integers). if register rs is less than rt , rd = 1; otherwise, rd =0. set on less than unsigned sltu rd, rs, rt compare contents of registers rt and rs (as unsigned, 32-bit integers). if register rs is less than rt , rd = 1; otherwise, rd =0. subtract sub rd, rs, rt subtract contents of registers rt from rs and place 32-bit result in register rd . trap on twos complement over?ow. subtract unsigned subu rd, rs, rt subtract contents of register rt from rs and place 32-bit result in register rd . do not trap on over?ow.
4-6 instruction set table 4.5 describes the shift instructions. table 4.5 shift instructions instruction format and description shift left logical sll rd, rt, shamt shift contents of register rt left by shamt bits, inserting zeros into low- order bits. place 32-bit result in register rd . shift left logical variable sllv rd, rt, rs shift contents of register rt left. low-order 5 bits of register rs specify the number of bits to shift. insert zeros into low-order bits of rt and place 32-bit result in register rd . shift right arithmetic sra, rd, rt, shamt shift contents of register rt right by shamt bits, sign extending the high-order bits. place 32-bit result in register rd . shift right arithmetic variable srav rd, rt, rs shift contents of register rt right. low-order 5 bits of register rs specify the number of bits to shift. sign extend the high-order bits of rt and place 32-bit result in register rd . shift right logical srl rd, rt, shamt shift contents of register rt right by shamt bits, inserting zeros into high-order bits. place 32-bit result in register rd . shift right logical variable srlv rd, rt, rs shift contents of register rt right. low-order 5 bits of register rs specify the number of bits to shift. insert zeros into high-order bits of rt and place 32-bit result in register rd .
instruction set 4-7 table 4.6 describes the multiply/divide instructions. table 4.6 multiply/divide instructions instruction format and description divide div rs, rt divide contents of registers rs by the contents of rt as twos complement values. place the 32-bit quotient in special register entrylo and the 32-bit remainder in entryhi. divide unsigned divu rs, rt divide contents of registers rs by the contents of rt as unsigned values. place the 32-bit quotient in special register entrylo and the 32-bit remainder in entryhi. move from hi mfhi rd move contents of special register entryhi to register rd . move from lo mflo rd move contents of special register entrylo to register rd . move to hi mthi rs move contents of register rs to special register entryhi. move to lo mtlo rs move contents of register rd to special register entrylo. multiply mult rs, rt multiply contents of registers rs and rt as twos complement values. place the 64-bit results in special registers entryhi and entrylo . (the entrylo and entryhi registers are read/write registers that access the tlb.) multiply unsigned multu rs, rt multiply contents of registers rs and rt as unsigned values. place 64-bit results in special registers entryhi and entrylo.
4-8 instruction set table 4.7 describes the extended computational instructions. table 4.7 extended computational instructions instruction format and description add circular immediate addciu rt, rs, immediate the 16-bit immediate is sign extended and added to the contents of general register rs , with the result masked by the value in cp0s cmask register according to the formula: rt = (rs 31...cmask ||(rs + signextended_imed) cmask - 1...0) find first clear bit ffc rd, rs starting at the most signi?cant bit in register rs , ?nd the ?rst bit which is set to 0, and return the bit number in register rd . if no bit is set, return with all bits of rd set to 1. find first set bit ffs rd, rs starting at the most signi?cant bit in register rs , ?nd the ?rst bit which is set to 1, and return the bit number in register rd . if no bit is set, return with all bits of rd set to 1. maximum max rd, rs, rt compare the contents of registers rs and rt as twos complement values. the larger value is stored in register rd . minimum min rd, rs, rt compare the contents of registers rs and rt as twos complement values. the smaller value is stored in register rd . multiply/add madd rs, rt multiply contents of registers rs and rt as twos complement values. add 64-bit results to the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. (the entrylo and entryhi registers are read/write registers that access the tlb.) multiply/add unsigned maddu rs, rt multiply contents of registers rs and rt as unsigned values. add 64-bit results to the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. multiply/subtract msub rs, rt multiply contents of registers rs and rt as twos complement values. subtract the 64-bit results from the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. multiply/subtract unsigned msubu rs, rt multiply contents of registers rs and rt as unsigned values. subtract the 64-bit results from the contents of the entrylo register and entryhi register, and place the results in entrylo and entryhi. (sheet 1 of 2)
instruction set 4-9 table 4.8 describes the jump instructions. select and shift left selsl rd, rs, rt using register rs and rt as a 64-bit register pair, and the contents of the cp0s rotate register as the shift count, shift the register pair rs | rt left the number of bits speci?ed in the rotate register, and place the most signi?cant 32-bit value in result register rd . select and shift right selsr rd, rs, rt using register rs and rt as a 64-bit register pair, and the contents of the cp0s rotate register as the shift count, shift the register pair rs | rt right the number of bits speci?ed in the rotate register, and place the least signi?cant 32-bit value in result register rd . table 4.7 extended computational instructions (cont.) instruction format and description (sheet 2 of 2) table 4.8 jump instructions instruction format and description jump j target shift 26-bit target address left two bits, combine with four high-order bits of pc, and jump to address with a one-instruction delay. jump and link jal target shift 26-bit target address left two bits, combine with four high-order bits of pc, and jump to address with a one-instruction delay. place address of instruction following delay slot in r31 (link register). jump and link register jalr rs, rd jump to address contained in register rs with a one-instruction delay. place address of instruction following delay slot in rd . jump register jr rs jump to address contained in register rs with a one-instruction delay.
4-10 instruction set table 4.9 describes the branch instructions. table 4.9 branch instructions instruction format and description branch on equal 1 beq rs, rt, offset branch to target address if register rs is equal to register rt . branch on greater than or equal to zero bgez rs, offset branch to target address if register rs is greater than or equal to 0. branch on greater than or equal to zero and link bgezal rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is greater than or equal to 0. branch on greater than zero bgtz rs, offset branch to target address if register rs is greater than 0. branch on less than or equal to zero blez rs, offset branch to target address if register rs is less than or equal to 0. branch on less than zero bltz rs, offset branch to target address if register rs is less than 0. branch on less than zero and link bltzal rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is less than 0. branch on not equal bne rs, rt, offset branch to target address if register rs does not equal register rt . 1. all branch-instructions target addresses are computed as follows: add the address of instruction in the delay slot and the 16-bit offset (shifted left two bits and sign-extended to 32 bits). all branches occur with a delay of one instruction.
instruction set 4-11 table 4.10 describes the branch likely instructions. table 4.10 branch likely instructions instruction format and description branch on equal likely beql rs, rt, offset branch to target address if register rs is equal to register rt . branch on greater than or equal to zero likely bgezl rs, offset branch to target address if register rs is greater than or equal to 0. branch on greater than or equal to zero and link likely bgezall rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is greater than or equal to 0. branch on greater than zero likely bgtzl rs, offset branch to target address if register rs is greater than 0. branch on less than or equal to zero likely blezl rs, offset branch to target address if register rs is less than or equal to 0. branch on less than zero and link likely bltzall rs, offset place address of instruction following delay slot in register r31 (link register). branch to target address if register rs is less than 0. branch on less than zero likely bltzl rs, offset branch to target address if register rs is less than 0. branch on not equal likely bnel rs, rt, offset branch to target address if register rs does not equal register rt .
4-12 instruction set table 4.11 describes the trap instructions. table 4.11 trap instructions instruction format and description trap if equal teq rs, rt trap if register rs is equal to register rt . trap if equal immediate teqi rs, immediate trap if register rs is equal to the immediate value. trap if greater than or equal tge rs, rt trap if register rs is greater than or equal to register rt . trap if greater than or equal immediate tgei rs, immediate trap if register rs is greater than or equal to the immediate value. trap if greater than or equal immediate unsigned tgeiu rs, immediate trap if register rs is greater than or equal to the immediate value. trap if greater than or equal unsigned tgeu rs, rt trap if register rs is greater than or equal to register rt . trap if less than tlt rs, rt trap if register rs is less than register rt . trap if less than immediate tlti rs, immediate trap if register rs is less than the immediate value. trap if less than immediate unsigned tltiu rs, immediate trap if register rs is less than the immediate value. trap if less than unsigned tltu rs, rt trap if register rs is less than register rt . trap if not equal tne rs, rt trap if register rs is not equal to rt . trap if not equal immediate tnei rs, immediate trap if register rs is not equal to the immediate value.
instruction set 4-13 table 4.12 describes the special instructions. table 4.13 describes the cp0 instructions. table 4.12 special instructions instruction format and description breakpoint break initiate breakpoint trap, immediately transferring control to exception handler. system call syscall initiate system call trap, immediately transferring control to exception handler. table 4.13 cp0 instructions instruction format and description exception return 1 eret (r4000 mode) load the pc from errorepc(sr2 = 1:error exception) or epc(sr2=0:exception) and clear erl bit (sr2 = 1) or exl bit (sr2 = 0) in the status register. sr2 is status register bit[2]. move from cp0 mfc0 rt, rd load contents of cp0 register rd into cpu register rt . move to cp0 mtc0 rt, rd load contents of cpu register rt into cp0 register rd . restore from exception 1 rfe (r3000 mode) restore previous interrupt mask and mode bits of the status register into current status bits. restore old status bits into previous status bits. wait for interrupt waiti stop execution of instructions and place the processor in a power save (stall) condition until a hardware interrupt, nmi (nonmaskable interrupt), or reset is received. 1. eret and rfe cannot be legal at the same time. the one that is not legal causes a reserved instruction exception.
4-14 instruction set table 4.14 describes the cache maintenance instructions. table 4.14 cache maintenance instructions instruction format and description flush d-cache flushd flush d-cache. 256 stall cycles will be needed. flush i-cache flushi flush i-cache. 256 stall cycles will be needed. flush i-cache & d-cache flushid flush both i-cache and d-cache in 256 stall cycles. write back wb offset(base) write back a d-cache line addressed by offset + gpr[base]. this instruction applies to both d-cache sets.
cw4011 instruction set extensions 4-15 4.2 cw4011 instruction set extensions this section de?nes the cw4011 instruction set extensions. addciu add with circular mask immediate format syntax addciu rt, rs, immediate description the immediate ?eld of the instruction is sign extended and added to the contents of general register rs , the result is masked with the expanded value in special register cmask according to the equation shown below. the cmask register is cp0 register number 24, whose valid bits are [4:0]. the carries resulting from the addition of the sign extended offset are not propagated into the ?nal result beyond bit cmask - 1. operation t: sign_extend_immed = (immediate 15 ) 16 || immediate 15..0 gpr[rt] = gpr[rs] 31..cmask || (gpr[rs] + sign_extend_immed) cmask - 1..0 exceptions none 31 26 25 21 20 16 15 0 addciu rs rt immediate 011100 rs rt immediate
4-16 instruction set ffc find first clear bit format syntax ffc rd, rs description the contents of general register rs are examined starting with the most signi?cant bit. the bit number of the ?rst clear bit is returned in general register rd . if no bit is set, all ones are returned in rd . exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs 0 rd 0 ffc 000000 rs 0 rd 00000 001011
cw4011 instruction set extensions 4-17 ffs find first set bit format syntax ffs rd, rs description the contents of general register rs are examined starting with the most signi?cant bit. the bit number of the ?rst set bit is returned in general register rd . if no bit is set, all ones are returned in rd . exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs 0 rd 0 ffs 000000 rs 0 rd 00000 001010
4-18 instruction set flushd flush data cache format syntax flushd description flushd ?ushes all data cache lines and causes stall cycles for 256 clocks, regardless of the cache size. exceptions none 31 26 25 21 20 16 15 0 cache 0 flushd 0 101111 00000 00010 0
cw4011 instruction set extensions 4-19 flushi flush instruction cache format syntax flushi description flushi ?ushes all instruction cache lines and causes stall cycles for 256 clocks, regardless of the cache size. exceptions none 31 26 25 21 20 16 15 0 cache 0 flushi 0 101111 00000 00001 0
4-20 instruction set flushid flush instruction and data cache format syntax flushid description flushid ?ushes all data and instruction cache lines and causes stall cycles for 256 clocks, regardless of the cache size. exceptions none 31 26 25 21 20 16 15 0 cache 0 flushid 0 101111 00000 00011 0
cw4011 instruction set extensions 4-21 madd multiply add format syntax madd rs, rt description the contents of general register rs and the contents of general register rt are multiplied. both operands are treated as 32-bit twos complement values. when the operation is completed, the doubleword result is added to special register pair hi/lo. no over?ow exception occurs under any circumstances. this instruction is only available when the chip has multiplier-accumulator module hardware and mad/mul are set to one in the cache con?guration and control (ccc) register. madd executes in multiple cycles, depending on the number of signi?cant bits in the operands. refer to table 4.15 on page 4-31 . operation t: t <- (hi || lo) + (gpr[rs] * gpr[rt]) lo <- t31..0, hi <- t 63..32 exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt 0 0 madd 000000 rs rt 0 00000 011100
4-22 instruction set maddu multiply add unsigned format syntax maddu rs, rt description the contents of general register rs and the contents of general register rt are multiplied with both operands treated as 32-bit unsigned values. when the operation is completed, the doubleword result is added to special register pair hi/lo. no over?ow exception occurs under any circumstances. this instruction is only available when the chip has multiplier-accumulator module hardware and mad/mul are set to one in the ccc register. the instruction executes in multiple cycles, depending on the number of signi?cant bits in the operands. refer to table 4.15 on page 4-31 . operation t: t <- (hi || lo) + ((0||gpr[rs]) * (0||gpr[rt])) lo <- t31..0, hi <- t 63..32 exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt 0 0 maddu 000000 rs rt 0 00000 011101
cw4011 instruction set extensions 4-23 max maximum format syntax max rd, rs, rt description the source operands rs and rt are compared as twos complement values. the larger value is stored in the rd register. operation t: if gpr[rs] > gpr[rt] then gpr[rd] <- gpr[rs] else gpr[rd] <- gpr[rt] endif exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt rd 0 max 000000 rs rt rd 00000 101001
4-24 instruction set min minimum format syntax min rd, rs, rt description the source operands rs and rt are compared as twos complement values. the smaller value is stored in the rd register. operation t: if gpr[rs] < gpr[rt] then gpr[rd] <- gpr[rs] else gpr[rd] <- gpr[rt] endif exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt rd 0 min 000000 rs rt rd 00000 101000
cw4011 instruction set extensions 4-25 msub multiply subtract format syntax msub rs, rt description the contents of general register rs and rt are multiplied and both operands are treated as 32-bit twos complement values. when the operation is complete, the doubleword result is subtracted from special register pair hi/lo. no over?ow exception occurs under any circumstances. this instruction is only available when the chip has multiplier-accumulator module hardware and mad/mul are set to one in the ccc register. the instruction executes in multiple cycles, depending on the number of signi?cant bits in the operands. refer to table 4.15 on page 4-31 . operation t: t <- (hi || lo) - (gpr[rs] * gpr[rt]) lo <- t31..0, hi <- t 63..32 exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt 0 0 msub 000000 rs rt 0 00000 011110
4-26 instruction set msubu multiply subtract unsigned format syntax msubu rs, rt description the contents of general register rs and rt are multiplied and both operands are treated as 32-bit unsigned values. when the operation is completed, the doubleword result is subtracted from special register pair hi/lo. no over?ow exception occurs under any circumstances. this instruction is only available when the chip has multiplier-accumulator module hardware and mad/mul are set to one in the ccc register. the instruction executes in multiple cycles, depending on the number of signi?cant bits in the operands. refer to table 4.15 on page 4-31 . operation t: t <- (hi || lo) - ((0||gpr[rs]) * (0||gpr[rt])) lo <- t31..0, hi <- t 63..32 exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt 0 0 msubu 000000 rs rt 0 00000 011111
cw4011 instruction set extensions 4-27 selsl select and shift left format syntax selsl rd, rs, rt description the contents of general register rs and rt are combined to form a 64-bit doubleword. the doubleword is shifted left the number of bits speci?ed in the cp0 register rotate, and the upper 32 bits of the result are placed in general register rd . this rotate register is cp0 register number 23, with valid bits [4:0]. operation t: s <- rotate 4..0 gpr[rd] <- gpr[rs] 31 - s..0 || gpr[rt] 31..32 - s exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt rd 0 selsl 000000 rs rt rd 00000 000101
4-28 instruction set selsr select and shift right format syntax selsr rd, rs, rt description the contents of general register rs and rt are combined to form a 64-bit doubleword. the doubleword is shifted right the number of bits speci?ed in cp0 register rotate, and the lower 32 bits of the result are placed in general register rd . this rotate register is cp0 register number 23. valid bits are [4:0]. operation t: s <- rotate 4..0 gpr[rd] <- gpr[rs] s - 1..0 || gpr[rt] 31..s exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 special rs rt rd 0 selsr 000000 rs rt rd 00000 000001
cw4011 instruction set extensions 4-29 waiti wait for interrupt format syntax waiti description when this instruction is executed, the main processor clock stops and execution of instructions is halted. execution resumes when a hardware interrupt, nmi, or reset exception is received. while it is in wait mode, the processor is in a power saving mode, using very little current because the clock is turned off to most of the circuitry. waiti must be followed by two or more no-operation instructions, otherwise, the results may be unde?ned. refer to appendix a, programmers notes in the minirisc cw4011 superscalar microprocessor core technical manual for further information. exceptions none 31 26 25 21 20 16 15 11 10 6 5 0 cop0 0 0 0 waiti 010000 10000 00000 00000 00000 100000
4-30 instruction set wb write back data cache format syntax wb offset( base ) description eight words of the data cache line addressed by offset + gpr[base] are written back to memory if the line is dirty. upper bits of offset + gpr[base ] are ignored. exceptions none 4.3 cpu instruction opcode bit encoding tables 4.15 through 4.21 show the opcode bit encoding for cw4011 instructions. the following keys are referenced in the tables: 31 26 25 21 20 16 15 0 cache base wb offset 101111 base 00100 offset *rxf1 operation codes marked with *rxf1 cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture. *rxf2 operation codes marked with *rxf2 cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture. *rxf2 is separated from other reserved instructions for copz. these are not detected as reserved instruction codes that cause an exception on the r3000. the r4000 detects them. *rx40 an operation code marked with *rx40 causes a reserved instruction exception on r4000 and cw4011 processors (when in r4000 mode). it is used as a restore from exception (rfe) instruction on the r3000, lr33000, lr33300, and cw4011 in r3000 mode. *rx64 operation codes marked with *rx64 cause a reserved instruction exception. they are 64-bit instructions on r4000. *nrx operation codes marked with *nrx are invalid but do not cause reserved instruction exceptions in cw4011 implementations.
cpu instruction opcode bit encoding 4-31 x1 operation codes marked with x1 are originally extended instructions in cw4011 implementations. they are reserved instructions that cause an exception on r4000. x2 the operation code cache marked with x2 is valid only for cw4011 processors with cp0 enabled and causes a reserved instruction exception with cp0 disabled. bits [20:16] are subopcodes. they are instructions for cache maintenance, and the functions are not compatible with r4000. recommended mnemonics are flushi , flushd , flushid , and wb offset ( base ). undefined opcodes of cache instructions do not cause reserved instruction exception in cw4011 implementations. x3 operation codes marked with x3 are originally extended instructions in cw4011 implementations. they are used for 64-bit multiply and divide instructions on r4000. if the mul bit or mad bit in the ccc register is zero, they cause a reserved instruction exception. the ccc register is described in detail in section 3.3.1, ccc register, on page 3-5 . x4 operation codes marked with x4 cause a reserved instruction exception if the mul bit in the ccc register is zero. x5 the operation code eret marked with x5 is valid only on the r4000 and cw4011 in r4000 mode. x6 operation codes marked with x6 are coprocessor-3 instructions, which are not available on r4000. these are available on the r3000 and cw4011. table 4.15 cw4011 opcode bit encoding [28:26] opcode [31:29] 0 1 2 3 4 5 6 7 0 special regimm j jal beq bne blez bgtz 1 addi addiu slti sltiu andi ori xori lui 2 cop0 cop1 cop2 cop3 x6 beql bnel blezl bgtzl 3 *rx64 *rx64 *rx64 *rx64 addciu x1 *rxf1 *rxf1 *rxf1 4 lb lh lwl lw lbu lhu lwr *rx64 5 sb sh swl sw *rx64 *rx64 swr cache x2 6 ll lwc1 lwc2 lwc3 x6 *rx64 *rx64 *rx64 *rx64 7 sc swc1 swc2 swc3 x6 *rx64 *rx64 *rx64 *rx64
4-32 instruction set table 4.16 special opcode bit encoding [2:0] special function [5:3] 0 1 2 3 4 5 6 7 0 sll selsr x1 srl sra sllv selsl x1 srlv srav 1 jr jalr ffs x1 ffc x1 syscall break *rxf1 sync 2 mfhi x4 mthi x4 mflo x4 mtlo x4 *rx64 *rxf1 *rx64 *rx64 3 mult x4 multu x4 div x4 divu x4 madd x3 maddu x3 msub x3 msubu x3 4 add addu sub subu and or xor nor 5 min x1 max x1 slt sltu *rx64 *rx64 *rx64 *rx64 6 tge tgeu tlt tltu teq *rxf1 tne *rxf1 7 *rx64 *rxf1 *rx64 *rx64 *rx64 *rxf1 *rx64 *rx64 table 4.17 regimm opcode rt bit encoding [18:16] regimm rt [20:19] 0 1 2 3 4 5 6 7 0 bltz bgez bltzl bgezl *rxf1 *rxf1 *rxf1 *rxf1 1 tgei tgeiu tlti tltiu teqi *rxf1 tnei *rxf1 2 bltzal bgezal bltzall bgezall *rxf1 *rxf1 *rxf1 *rxf1 3 *rxf1 *rxf1 *rxf1 *rxf1 *rxf1 *rxf1 *rxf1 *rxf1
cpu instruction opcode bit encoding 4-33 table 4.18 cache x2 opcode rt bit encoding [18:16] cache x2 rt [20:19] 0 1 2 3 4 5 6 7 0 *nrx flushi x2 flushd x2 flushid x2 wb x2 *nrx *nrx *nrx 1 *nrx *nrx *nrx *nrx *nrx *nrx *nrx *nrx 2 *nrx *nrx *nrx *nrx *nrx *nrx *nrx *nrx 3 *nrx *nrx *nrx *nrx *nrx *nrx *nrx *nrx table 4.19 copz rs opcode bit encoding [23:21] copz rs [25:24] 0 1 2 3 4567 0 mfcz *rx64 cfcz *rxf2 mtcz *rx64 ctcz *rxf2 1 bc *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 2 copz (coprocessor de?ned instructions) 3 table 4.20 copz rt opcode bit encoding [18:16] copz rt [20:19] 0 1 2 3 4 5 6 7 0 bcf bct bcfl bctl *rxf2 *rxf2 *rxf2 *rxf2 1 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 3 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2 *rxf2
4-34 instruction set table 4.21 cp0 opcode bit encoding [2:0] cp0 function [5:3] 0 1234567 0 *nrx tlbr tlbwi *nrx *nrx *nrx tlbwr *nrx 1 tlbp *nrx *nrx *nrx *nrx *nrx *nrx *nrx 2 rfe rx40 *nrx *nrx *nrx *nrx *nrx *nrx *nrx 3 eret x5 *nrx *nrx *nrx *nrx *nrx *nrx *nrx 4 waiti x1 *nrx *nrx *nrx *nrx *nrx *nrx *nrx 5 *nrx *nrx *nrx *nrx *nrx *nrx *nrx *nrx 6 *nrx *nrx *nrx *nrx *nrx *nrx *nrx *nrx 7 *nrx *nrx *nrx *nrx *nrx *nrx *nrx *nrx
5-1 chapter 5 bus interface descriptions this chapter describes the LR4500 interface signals and associated buffer circuitry required for scbus signals. the chapter provides information on the following subjects: external interfaces C the mbus provides the interface between the LR4500 dram controller and the external dram array, see page 5-2 . C the lbus provides the interface between the sclc and devices on the lbus, see page 5-5 . C the phase-locked loop (pll) interface provides the interface between the pll clock generator and the cw4011 shell, see page 5-9 . C test-signal input pins allow lsi logic to test the LR4500, see page 5-10 . C a core monitor signal allows you to monitor the behavior of the cw4011 core, see page 5-11 . internal interfaces C the scbus interfaces between the cw4011 shell and the dramc and sclc, see page 5-11 . C external buffering required for certain scbus signals (see page 5-19 ). C the reset/interrupt interface between the cw4011 shell and the dramc and sclc, see page 5-22 . figure 5.1 shows the three major busesthe scbus, mbus, and lbus.
5-2 bus interface descriptions figure 5.1 LR4500 interfaces 5.1 external interfaces this section describes the LR4500 external interfaces: mbus, lbus, pll, test, and core monitor. each signal de?nition contains the mnemonic and the full signal name. active low signals have an n suf?x, for example, scresetn. active high signals have a p suf?x, for example, mdqmp. assert means to drive the signal true or active. deassert means to drive the signal false or inactive. 5.1.1 mbus interface figure 5.2 shows the 89 mbus signals that the LR4500 uses to connect the LR4500 dram controller to the synchronous drams in the main memory array. inputs and outputs are referenced to the LR4500 reference device and more speci?cally to the dram controller. LR4500 lbus devices dram controller cw4011 shell reference device lbus mbus scbus synchronous dram scbus/lbus converter described in described in described in pll cell system clock microprocessor lbus interface mbus interface scbus interface
external interfaces 5-3 figure 5.2 mbus interface map[11:0] multiplexed memory address bus output these multiplexed signals carry row and column addresses. mrasn strobes the row addresses into the drams, and mcasn strobes the column addresses. address bit assignment on page 6-4 provides detailed information about the address bus. during memory initialization, the dram controller uses map[11:0] to write the 12-bit mode register in each dram. mcasn memory column address strobe output the LR4500 asserts mcasn to strobe memory column addresses into the memory devices. scbus synchronous map[11:0] mdp[63:0] mcsn[1:0] mrasn mcasn mwen mdqmp[7:0] LR4500 dram cw4011 shell reference device dram array controller scbus/lbus converter mbus lbus
5-4 bus interface descriptions mcsn[1:0] memory chip select output mcsn[1:0] select between banks 0 and 1 in the dram array. the dram controller asserts mscn0 to select the drams that make up bank 0, and asserts mscn1 to select the drams in bank 1. if only one bank of drams is installed, the dram controller asserts mcsn0. mdp[63:0] memory data bus bidirectional this 64-bit bidirectional data bus carries data between the LR4500 and the memory array. the direction of data ?ow is controlled by mwen. mdqmp[7:0] memory data enable/mask output this is an 8-bit data mask used only during write opera- tions. when asserted, each bit of the mask selects one byte of data, as shown in the examples below, to enable write operations in individual bytes of the data word. 8-bit wide drams mask byte selected dram byte number mdqmp 7 mdp[63:56] 7 mdqmp 6 mdp[55:48] 6 mdqmp 5 mdp[47:40] 5 mdqmp 4 mdp[39:32] 4 mdqmp 3 mdp[31:24] 3 mdqmp 2 mdp[23:16] 2 mdqmp 1 mdp[15:8] 1 mdqmp 0 mdp[7:0] 0 16-bit wide drams mask byte selected dram byte number mdqmp 7 mdp[63:56] 3 (upper byte) mdqmp 6 mdp[55:48] 3 (lower byte) mdqmp 5 mdp[47:40] 2 (upper byte) mdqmp 4 mdp[39:32] 2 (lower byte) mdqmp 3 mdp[31:24] 1 (upper byte) mdqmp 2 mdp[23:16] 1 (lower byte) mdqmp 1 mdp[15:8] 0 (upper byte) mdqmp 0 mdp[7:0] 0 (lower byte)
external interfaces 5-5 mrasn memory row address strobe output the LR4500 asserts mrasn to strobe memory row addresses into the memory devices. mwen memory write enable output the LR4500 asserts mwen to enable a write operation and deasserts mwen to enable a read operation. 5.1.2 lbus interface figure 5.3 shows the 75 lbus signals that connect the sclc in the LR4500 with external lbus devices. the LR4500 functions as the bus master to access external devices on the lbus, such as boot-rom, serial devices, and the ethernet controller. these lbus devices can also function as bus master to access the dram through the sclc and the dramc.
5-6 bus interface descriptions figure 5.3 lbus interface inputs and outputs on the lbus are referenced to the LR4500. since either the LR4500 or an lbus device can be bus master, some signals that are typically unidirectional, such as the read signal lrdn, are bidirectional on the lbus. when the LR4500 is bus master and asserts lrdn, it enables a read operation in one of the lbus devices. when an lbus device is bus master, it can assert lrdn to read data from the dram. lap[31:2] lbus address bus bidirectional when the LR4500 is master of the lbus, it outputs the address that is used to access one of the devices on the lbus. if one of the devices on the lbus is bus master, it outputs to the LR4500 the address used to access the dram. lbus devices scbus strap low lchalfn lclkp lap[31:2] ldp[31:0] lben[3:0] lrdn ladsn lrdyn lrtyn lholdp lhldap lbus LR4500 dram controller cw4011 shell reference device scbus/lbus converter mbus lcresetn
external interfaces 5-7 ladsn lbus address strobe bidirectional this signal strobes the lbus addresses. the bus master asserts it at the ?rst lclkp cycle of a transaction. when the LR4500 asserts lhldap and grants bus ownership to an lbus master device, the master device inputs this signal to the LR4500. when the LR4500 is the bus master, it inputs this signal to the lbus device. the initiating device must synchronize this signal to the lbus clock, lclkp. lben[3:0] lbus byte enable signals bidirectional the master device drives these signals active (low), to enable data on the lbus, as shown below. the read/write signal, lrdn, controls the direction of data ?ow. byte operations, that is operations where individual bytes are selected, occur only during write transactions. lchalfn lbus clock speed input this signal sets the clock speed for the lbus. when a device on the lbus drives this signal high, it divides the scbus clock (sclkp) by two, and the LR4500 outputs a clock signal (lclkp) that is one half the frequency of sclkp. when the signal is low, it divides the sclkp by four, and the LR4500 outputs lclkp at one quarter the frequency of sclkp. lclkp lbus clock output this output is derived from the scbus clock, sclkp. lbus clock rate is either half or quarter the clock rate of sclkp, depending on the state of the lchalfn input to the LR4500. lcresetn lclk divider reset input lsi logic uses this signal for testing. you can deassert the signal by strapping it high. byte enable signal byte bits byte number lben 3 ldp[31:24] byte 3 lben 2 ldp[23:16] byte 2 lben 1 ldp[15:8] byte 1 lben 0 ldp[7:0] byte 0
5-8 bus interface descriptions ldp[31:0] lbus data bus bidirectional this 32-bit bidirectional data bus transfers data between the devices on the lbus and the LR4500. the read/write signal, lrdn , controls the direction of data ?ow on the lbus. lhldap lbus hold acknowledge output the LR4500 asserts this signal in response to an lholdp input from an lbus device. when asserted, the signal grants a bus hold and allows the lbus device to take bus ownership. lholdp lbus hold request input an lbus device asserts lholdp to request ownership of the lbus. the initiating device must synchronize the signal to the rising edge of lclkp. lrdn lbus read bidirectional the master device asserts this signal to enable a read operation and deasserts it to enable a write operation. when the LR4500 asserts lhldap and grants bus ownership to an lbus master device, the master device inputs this signal to the LR4500. when the LR4500 is the bus master, it inputs this signal to the lbus device. lrdyn lbus data ready bidirectional when it is asserted, this signal terminates a transaction. when the LR4500 asserts lhldap and grants bus ownership to an lbus device, the LR4500 inputs this signal to the LR4500. when the LR4500 is the bus master, the lbus device inputs this signal to the LR4500. the initiating device must synchronize this signal to the lbus clock, lclkp. lrtyn lbus retry input when an lbus slave device asserts this signal and inputs it to the LR4500, the LR4500 temporarily aborts any transaction in progress and initiates the transaction again later. the initiating lbus device must synchronize the signal to the rising edge of lclkp.
external interfaces 5-9 5.1.3 phase-locked loop (pll) clock signals the pll circuit generates the clock inputs for the cw4011 shell and for the other modules that are part of the LR4500. the test signals associated with the pll circuit are not for general use and are therefore deasserted by strapping them low if they are active-high signals, and strapping them high if they are active-low signals. this section describes the pll signals. pll clock circuit on page 2-5 provides further information on this subject. pllagnd pll analog ground ground this is the analog ground for the pll circuit. you must connect an rc (resistor/capacitor) circuit for the pll ?lter between pins plllp2p and pllagnd on the pll circuit, as shown in figure 2.2 ,on page 2-6 . pllctop test counter open output from pll circuit this signal is an open pin on the board. pllctrn test counter reset input to pll circuit this signal is strapped low. pllenp vco enable(1)/disable(0) strapped input this input to the pll circuit enables the pll circuit when the input is active (high), and disables the pll circuit when it is low. the signal is strapped high on the main circuit board so that the pll circuit is always enabled. plliddtp test enable input input to pll circuit this signal enables test inputs when it is active (high). it is strapped low on the main circuit board. plllp2p vco input and loop filter filter pin you must connect an rc (resistor/capacitor) circuit for the pll ?lter between pins plllp2p and pllagnd on the pll circuit, as shown in figure 2.2 ,on page 2-6 . pllrefp system clock reference input this is the system reference clock that is input to the cw4011 by the pll circuit. plltdp test data (clock) input to pll circuit this signal is strapped low.
5-10 bus interface descriptions plltstp test enable input to pll circuit this signal is strapped low, which means that testing is generally disabled. pllvdd pll power input to pll circuit this signal provides vdd power. pllvss pll ground ground this is the ground for the pll circuit. 5.1.4 test signals there are nine pins on the LR4500 chip that allow designers at lsi logic to test the device using an lsi logic tester. when the pins are not being used for testing, you must deassert all inputs by strapping active-high signals low and active-low signals high. you must leave all outputs unconnected. inputs are referenced to and outputs are referenced from the LR4500. iceclkp ice serial bit clock rate x16 input the iceport requires an off-chip pin with a clock that runs at 16 times the serial transmit/receive rate. icerxp rx serial bit receive input this signal carries the iceport uart (universal asynchronous receiver/transmitter) serial input data stream. icetxp tx serial bit transmit output this output sends out the iceport uart serial data stream. paramoutp parametric nand treelsi logic use only output this output is used to check the parametric nand tree. it is reserved for factory use during testing. leave it unconnected on the board. scancrip cw4011 core scanlsi logic use only input strap this signal low on the board. scancrop cw4011 core scanlsi logic use only output leave this signal unconnected.
internal interface 5-11 scanenbp global LR4500 scan enablelsi logic use only input strap this signal low on the board. testmp test mode for scanlsi logic use only input this input is reserved for factory use during testing . strap it low on the board. zstaten global 3-state controllsi logic use only input this input is reserved for factory use during testing . strap it high on the board. 5.1.5 cw4011 core monitor signal the LR4500 has one pin that enables you to monitor the behavior of the cw4011 core. mclkp internal clock monitor output this output from the internal clock allows you to check the clock phase. when you are not using the pin to check the clock, the output should be unconnected. 5.2 internal interface this section describes the LR4500 internal interfaces: scbus, external buffering required for certain scbus signals, and the reset/interrupt interface. each signal de?nition contains the mnemonic and the full signal name. active low signals have an n suf?x, for example, scresetn. active high signals have a p suf?x, for example, mdqmp. assert means to drive the signal true or active. deassert means to drive the signal false or inactive. 5.2.1 scbus interface the scbus interface provides the link between cw4011 core elements that are part of the cw4011 shell and the dramc and sclc modules that are external to the cw4011 shell, but are part of the LR4500 reference device. figure 5.4 shows a simpli?ed view of this interface.
5-12 bus interface descriptions in the interface between the cw4011 shell and the sclc, either module can function as the bus master or bus slave. in the interface between the cw4011 and the dram controller, the cw4011 shell is always the master. figure 5.4 also shows the cache invalidation signals (icinvsn and dcinvsn) that are input to the cw4011 shell from the sclc, and the address enable, write enable, and bus ready signals that interface between the dramc and the sclc. the signals described in this section are shown in figure 5.4 .
internal interface 5-13 figure 5.4 scbus interface dcinvsn d-cache invalidation strobe input to shell from sclc the sclc asserts this signal to indicate that the cinvap invalidation address bus is valid for d-cache and there is a need for a snooping sequence. if the cache tag is not coincident with higher address bits, the line is not invalidated. sctpwn sclockn sctbstn scben[7:0] sctssn scdoen scdp[63:0] scaoen scap[31:0] schgtn sctsen scbrdyn scbpwan scbrtyn scberrn scb32n schrqn dram controller scbus/lbus controller cw4011 shell slaoen slwrn drrdyn dcinvsn icinvsn
5-14 bus interface descriptions drrdyn dram ready output from dramc to sclc the dramc asserts drrdyn when the current dram transaction is terminated, indicating that the bus is available. the signal remains active (low) until the next transaction starts. the dramc outputs the signal to the sclc, which merges drrdyn with its own bus ready signal ( page 5-19 ) and drives scbrdyn, which is output to the cw4011 shell. icinvsn i-cache invalidation strobe input to shell from sclc the sclc asserts this signal to indicate that the cinvap invalidation address bus is valid for i-cache and there is a need for a snooping sequence. if the cache tag is not coincident with higher address bits, the line is not invalidated. scap[31:0] address bus bidirectional between shell and sclc input to dramc the cw4011 asserts the signals on this bus and outputs them to the sclc or the dramc. the lbus master can also assert scap[31:0] and output the address to the cw4011 shell through the sclc. scap[31:0] is the 32-bit address bus used for instruction fetch and data read/write operations. the bus signals are valid only when the address output enable signal, scaoen, is asserted. the enable signal remains valid throughout the operation until scbrdyn, scbrtyn, or scberrn is asserted. scaoen address output enable output from shell to dramc the cw4011 asserts this signal, to indicate that the address bus lines, scap[31:0], are valid. the signal remains active throughout the bus transaction. scaoen also enables sctbstn, sctben, and sctpwn. this signal is never valid at the same time as slaoen (the address output enable signal output from the sclc shell to the dramc ( page 5-19 ). when testmp is asserted, scaoen is asserted. other address output enable signals must be deasserted when testmp is asserted.
internal interface 5-15 scb32n 32-bit bus width sizing input to shell from sclc the external lbus slave asserts scb32n to indicate that the scbus needs 32-bit bus sizing. the cw4011 core samples this signal on the rising edge of the clock that synchronizes the scbus ready signal, scbrdyn. if scb32n is asserted for a 64-bit transaction, which is a doubleword transaction or part of a burst transaction, the bus interface unit in the cw4011 core generates a subsequent 32-bit word transaction and packs data to 64 bits for a read transaction or unpacks data to 32 bits for a write transaction. scben[7:0] byte enable bidirectional between shell and sclc and input to dramc scben[7:0] indicates which byte positions are valid for a read or write transaction. the cw4011 asserts the signals and outputs them to the sclc or the dramc. the lbus device can also assert the signals and input them to the cw4011 through the sclc. only one of the signals is asserted during a byte read or byte write transaction. all signals are asserted for a doubleword or burst transaction. sctben signal valid byte positions 0 scdop[7:0] 1 scdop[15:8] 2 scdop[23:16] 3 scdop[31:24] 4 scdop[39:32] 5 scdop[47:40] 6 scdop[55:48] 7 scdop[63:56] all doubleword or burst transaction
5-16 bus interface descriptions scberrn bus error input to shell from sclc the lbus master device asserts scberrn to terminate the current transaction when a bus error occurs. if scbrdyn, or the bus retry signal, scbrtyn, is asserted at the same time as scberrn, scberrn has higher priority. scberrn is reported to the cp0, which in turn generates an exception. scbpwan bus in-page write accept input to shell from dramc the dramc asserts scbpwan to indicate that it accepts in-page write transactions. the cw4011 samples the signal on the rising edge of the clock that synchronizes scbrdyn. if the cw4011 has not asserted sctpwn, asserting or deasserting scbpwan has no signi?cance. scbrdyn bus ready input to shell from sclc the sclc asserts scbrdyn when the current transaction is terminated, indicating that the scbus is available. the signal remains active (low) until the next transaction starts. the sclc deasserts the signal to indicate that the scbus is not available. the sclc receives a bus-ready signal, drrdyn, from the dramc ( page 5-19 ), merges drrdyn with the sclc bus ready signal, and drives scbrdyn, which is output to the cw4011 shell. scbrtyn bus retry input to shell from sclc the lbus master device asserts scbrtyn when the current transaction has been terminated unsuccessfully and must be retried later. the control state goes back to the idle state, then all bus requests are arbitrated again. if there are no higher priority requests and the lbus master has asserted sctsen, there is one idle state between the ?rst transaction and a retry transaction. if scbrdyn and scbrtyn are asserted at the same time, scbrtyn has the higher priority. scdp[63:0] data bus bidirectional between shell, sclc, and dramc scdp[63:0] are the data bus signals. they are output from the cw4011 shell for data read/write operations and for data write back to the d-cache. they are input to the shell for data read and instruction fetch transactions. the
internal interface 5-17 cw4011 shell samples the signals on the rising edge of the clock when scbrdyn is asserted. the signals are valid throughout a write transaction in which the cw4011 writes to dram through the dramc, or the lbus device writes to the cw4011 or dramc through the sclc. byte ordering is little endian. scdoen data output enable output from shell to sclc and dramc the cw4011 asserts scdoen throughout a write transaction and outputs it to the sclc or the dramc. the signal indicates that the current transaction is a write transaction, and it also enables data output. it performs the same function for a cw4011 write transaction to dram that slwrn ( page 5-19 ) performs for an sclc write transaction to dram. when testmp is asserted, scdoen is asserted. other data output enables must be deasserted when testmp is asserted. schgtn bus hold grant output from shell to sclc the cw4011s bus interface unit enters the hold state and asserts schgtn to indicate that it is releasing scbus ownership in response to a bus hold request (schrqn) from one of the devices on the lbus. schrqn bus hold request input to shell from sclc schrqn indicates that a device on the lbus is requesting ownership of the scbus. bus hold request has the highest priority during bus arbitration. however, it cannot break continuous transactions of in-page writes and burst read/write transactions if those transactions are supported by an asserted sctsen. in such a case, schrqn must wait until sctsen is deasserted. sclockn bus lock output from shell to sclc the cw4011 asserts sclockn to indicate that it wishes to lock the scbus and restrict ownership. the cw4011 asserts the signal when a read transaction is started by executing a load link instruction in an uncached area or a write through cached area. it deasserts the signal just before a write transaction is started by executing a store conditional instruction. during read and write transactions, the cw4011 asserts the signal continuously, preventing ownership from changing during one of these transactions. if a store conditional
5-18 bus interface descriptions transaction hits the d-cache in a write back cached read while sclockn is asserted, an incorrect condition exists, and the cw4011 deasserts sclockn without completing any bus transactions. sctbstn burst transaction output from shell to dramc the cw4011 asserts sctbstn and outputs it to the dramc to indicate that a transaction is taking place during which four doublewords will be moved, and that the ?rst doubleword is currently being moved. the cw4011 deasserts the signal after the ?rst word has been transferred and during singleword transactions. sctpwn next transaction is in-page write output from shell to dramc the cw4011 asserts this signal to indicate that the next transaction is in the same dram page as the current transaction, as de?ned in the con?guration register. when the cw4011 asserts sctpwn, a maximum of four write transactions take place one after the other, even if there is an instruction fetch request or data read request. if there are four continuous write transactions, the cw4011 asserts sctpwn from the ?rst through the last (fourth) transaction. the cw4011 asserts sctpwn from the beginning of one in-page write transaction to the end of that transaction. the write buffer in the cw4011s lsu checks to see if the subsequent write request is in the same page. sctsen transaction start enable input to shell from sclc sctsen enables or disables a new scbus transaction. transaction requests are arbitrated only when sctsen is asserted. during the time sctsen is deasserted, the cw4011 cores bus interface unit repeats the idle state. if it is necessary to insert an idle cycle between two transactions, the lbus device may deassert sctsen then assert it when scbrdyn is asserted. sctssn transaction start strobe output from shell to sclc the cw4011 asserts sctssn for one clock cycle at the beginning of a transaction to indicate that a transaction has started. if the next transaction begins immediately, the cw4011 asserts sctssn continuously.
internal interface 5-19 slaoen address output enable output from sclc to dramc the sclc asserts this signal to indicate that the address bus lines, scap[31:0], are valid. the signal remains active throughout the bus transaction. scaoen also enables sctbstn, sctben, and sctpwn. this signal is not valid at the same time as scaoen, which is the address output enable signal output from the cw4011 shell to the sclc described on page 5-14 . slwrn sclc write enable output from sclc to dramc the sclc asserts this signal throughout a dram write operation and outputs it to the dramc. it performs the same function for a cw4011 write transaction to dram that scdoen ( page 5-17 ) performs for an sclc write transaction to dram. 5.2.2 external buffering for scbus signals you must provide external buffering for certain scbus signals, including: address bus scap[31:0] address output enable signals scaoen and slaoen sc data bus scdp[63:0] data output enable scdoen scbus byte enable scben[7:0] figure 5.5 shows an example of a buffer con?guration in which the bidirectional address bus is buffered at the sclc and cw4011 ends by bts4a*32 3-state buffers. when the cw4011 asserts scaoen, the signal enables the buffer at the cw4011 end. when the sclc asserts slaoen, the signal enables the buffer at the sclc end. during device scan test, cw4011 buffers should drive the bus. when testmp is asserted the output enable signal, scaoen, is asserted. other address output enable signals must be deasserted.
5-20 bus interface descriptions figure 5.5 buffering for scap[31:0] address bus figure 5.6 shows an example of a buffer con?guration in which the sc data bus is buffered at the sclc and cw4011 ends by bts4a*64 3-state buffers. when the cw4011 asserts scdoen, the signal enables the buffer at the cw4011 end. when the sclc asserts sldoen, the signal enables the buffer at the sclc end. a bts4a*64 buffer also buffers the data output from the dramc. this buffer is enabled when the dramc asserts drdoen. during device scan test, the cw4011 buffer should drive the bus. when testmp is asserted, scdoen is asserted and other address output enables must be deasserted. cinvap[31:5] scaop[31:0] scaoen cw4011 shell draip[31:0] slaip[31:0] slaop[31:0] slaoen sclc dramc scap[31:0] buffer bts4a*32 buffer bts4a*32 bus holder bhd1a*32 testmp testmp
internal interface 5-21 figure 5.6 buffering for scdp[63:0] data bus figure 5.7 shows an example of a buffer con?guration in which the sc byte enable signals, sctben[7:0], are buffered at the sclc and cw4011 ends by bts4a*8 3-state buffers. when the cw4011 asserts scaoen, the signal enables the buffer at the cw4011 end. when the sclc asserts slaoen, the signal enables the buffer at the sclc end. figure 5.7 buffering for scben[7:0] byte enable dramc scdip[63:0] scdop[63:0] scdoen cw4011 shell drdip[63:0] sldip[63:0] sldop[63:0] sldoen sclc scdp[63:0] buffer bts4a*64 buffer bts4a*64 bus holder bhd1a*64 drdop[63:0] drdoen buffer bts4a*64 testmp testmp sctben[7:0] scaoen cw4011 shell drbein[7:0] slbein[7:0] slbeon[7:0] slaoen sclc buffer bts4a*8 buffer bts4a*8 bus holder bhd1a*8 scben[7:0] dramc testmp testmp
5-22 bus interface descriptions 5.2.3 cw4011 shell reset/interrupt interface figure 5.8 shows the internal interface that links the cw4011 shell, the sclc, and the dramc to provide the reset and interrupt signals required by cp0. figure 5.8 shell reset/interrupt interface bendn big endian (strap input) input to shell this input affects the byte positions for sizing and load/store data alignment. when the input is low (asserted), the cw4011 works with big endian byte ordering. when high, byte ordering is little endian. exvap[31:2] external vectored interrupt address input to shell from sclc the cw4011 shell accepts the external vectored interrupt address when the sclc asserts exvapen. the cw4011 writes the address directly into the program counter. the address bus must remain stable until exvapen is asserted. cw4011 shell sexint[5:0] snmin swresetn scresetn pin inputs scbus/lbus converter dram controller frcmn bendn exvintn exvap[31:2] exvaen
internal interface 5-23 exvapen exvap enable output from shell to sclc this is the enable signal for the vectored interrupt address. the cw4011 asserts this signal to acknowledge the address. exvintn external vectored input input to shell from sclc the sclc drives this signal. when the cw4011 shell receives the signal, it generates an external vectored interrupt exception. frcmn force cache miss (strap input) input to shell this input is used for system debug. under normal operating conditions, you should deassert frcmn by strapping it high. to use it for debug, you should assert it by tying it low. when low, the signal forces a cache miss for the i-cache and the d-cache in the cw4011 shell. the cw4011 treats this event as an access to an uncached area. the cw4011 can then read and write all instructions and data as uncached, regardless of the memory segment and the mmu. sexintn[5:0] external interrupt input signals [5:0] input to shell the sclc asserts one of the sexint signals to cause the cp0 in the cw4011 core to generate an interrupt exception. the assertion is registered in the ip ?eld of the cw4011 cause register. the sclc should continue to assert the signals until the exception routine has serviced the interrupt. the cw4011 does not recognize interrupts if the interrupt enable bit in the status register is not set. the cw4011 can therefore disable individual interrupt inputs by clearing the related bits. however, the interrupt inputs are still registered in the ip ?eld of the cause register. external interrupt input signals [5:0] are synchronized to the system clock, sclkp, in the sclc. the minirisc cw4011 superscalar microprocessor core technical manual provides information about the cw4011 cp0 registers.
5-24 bus interface descriptions scresetn cold reset input to shell this input initiates a cold reset for the LR4500. inside the LR4500, this signal is synchronized to the system clock, sclkp. the LR4500 enters the cold reset condition when the sclc asserts scresetn. cp0 initiates a cold reset exception when the sclc deasserts scresetn. snmin nonmaskable interrupt input to shell this input is synchronized in the sclc to the system clock, sclkp. when the sclc asserts this signal, the cw4011 recognizes a nonmaskable interrupt. the cp0 then generates a nonmaskable interrupt exception (0xbfc0 0000). swresetn warm reset input to shell this input initiates a warm reset for the LR4500. this signal is synchronized to the system clock, sclkp inside the LR4500. the LR4500 enters the warm reset condition when the sclc asserts swresetn. cp0 initiates a cold reset exception when the sclc deasserts swresetn.
6-1 chapter 6 dram controller and memory bus this chapter describes the synchronous dram controller and the memory bus. it de?nes: dram types compatible with the LR4500 on page 6-1 address space available for the dram on page 6-1 memory interface on page 6-2 memory address bit assignment on page 6-4 dram controller con?guration register on page 6-5 dram mode register on page 6-10 dram refresh requirements, and the dram controller refresh register and refresh counter on page 6-12 dram commands on page 6-14 initializing the dram on page 6-15 6.1 dram types and available dram address area the LR4500 microprocessor reference device interfaces directly to synchronous drams, without any glue logic, through a 64-bit memory data bus. when the dram is arranged in two banks, the chip select signals, mcsn[1:0], select between the two banks. table 6.1 shows different dram con?gurations and the address ranges assigned to the memory banks. there is no programmable feature that de?nes the dram size and con?guration. the utility setup/bootstrap
6-2 dram controller and memory bus program should check the amount of installed dram when the system is initially powered up. 6.2 memory interface figure 6.1 shows the interface between the LR4500 mbus and the drams. in the example shown, eight dram devices with a 16-bit data bus are arranged in two memory banks, providing 16 mbytes of memory. this is the con?guration shown in line 2 of table 6.1 . note that this con?guration does not have continuous memory space. a clock-delay tap provides the clock input for the drams. the clock enable (cke) inputs to the drams are tied high, which means that they are always asserted. the LR4500 selects between bank 0 and bank 1 of the dram by means of the chip select signals, mcsn[1:0]. it asserts mcsn[0] to select the four drams in bank 0, and mcsn[1] to select the four drams in bank 1. the LR4500 distributes address (map[11:0]), row address strobe and column address strobe (mras and mcas), and the write enable signal (mwen) to all drams. data (mdp[63:0]) and the data mask table 6.1 dram con?gurations dram type number of banks number of drams memory size bank 0 address range bank 1 address range 1 m x 16 1 4 8 mbyte 0x0000 0000 C 0x007f ffff none 1 m x 16 2 8 16 mbyte 0x0000 0000 C 0x007f ffff 0x0200 0000 C 0x027f ffff 2 m x 8 1 8 16 mbyte 0x0000 0000 C 0x00ff ffff none 2 m x 8 2 16 32 mbyte 0x0000 0000 C 0x00ff ffff 0x0200 0000 C 0x02ff ffff 4 m x 4 1 16 32 mbyte 0x0000 0000 C 0x01ff ffff none 4 m x 4 2 32 64 mbyte 0x0000 0000 C 0x01ff ffff 0x0200 0000 C 0x03ff ffff
memory interface 6-3 (mdqmp[7:0]) are distributed to each byte in the dram array, with mdqmp[7] masking byte 7 (bits [63:56]), and so forth. figure 6.1 LR4500 interface with dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram csn rasn casn wen a[11:0] udqm ldqm dq[15:0] cke clk x 16 dram [7] [6] [5] [4] [3] [2] [1] [0] [63:48] [47:32] [31:16] [15:0] mdqmp[7:0] mdp[63:0] map[11:0] mrasn mcasn mwen mcsn[1] mcsn[0] sclkp clock delay tap system clock source LR4500 high bank 0 bank 1 unused taps
6-4 dram controller and memory bus 6.3 address bit assignment the dram controller in the LR4500 derives the dram addresses, map[11:0], from the 32 scbus address bits output by the bus master, which may be the cw4011 core or the sclc module. the controller outputs the address bits on the mbus, assigning the bits as shown in figure 6.2 . the byte select signals, mdqmp[7:0], are derived directly from the byte enable signals, sctben[7:0]. figure 6.2 scbus dram address bit assignment the map[11:0] 12-bit address bus multiplexes row and column addresses. table 6.2 lists the scbus address and mbus address bit assignments. 0000 00 31 26 25 c9 cs c8 r11 r10 r8 r7 r6 r5 r4 r3 r2 r1 r0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 c7 10 c6 9 c5 c4 8 7 c3 6 c2 5 c1 4 c0 3 x x x 2 0 x x x c8c7c6c5c4c3c2c1c0 scbus address bits x x c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 x x x x c7 c6 c5 c4 c3 c2 c1 c0 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 column addresses for 4-bit wide drams column addresses for 8-bit wide drams column addresses for 16-bit wide drams row addresses for all drams 109876543210 mbus address bits cs = 1 enables mcsn[1] to select bank 1 cs = 0 enables mcsn[0] to select bank 0 dont r9 r11 11 x indicates that the bit is not used in this con?guration sdram is selected when bits [31:26] are set to 0 care x indicates a dont care situation
dram controller con?guration register 6-5 6.4 dram controller con?guration register the dram controller con?guration register allows you to con?gure various features of the dram. the virtual and physical addresses for the register are shown below: figure 6.3 shows the format recommended for the dram controller con?guration register. figure 6.3 dram controller con?guration register format table 6.2 scbus address and mbus address bit assignment scbus address bits address bit function mbus address bits sctben[7:0] byte selection during write operations mdqmp[7:0] scap[10:3] 1 1. these bits are used for column addresses in 16-bit wide drams. they are used in conjunction with sc[23] for 8-bit wide drams, and with sc[24:23] for 4-bit wide drams. since sc[10:3] supply column addresses, the dram page size is 1 kbyte for all drams. column addresses c[7:0] map[7:0] scap[22:12] row addresses r[11:0] map[11:0] scap[24:23] column addresses c[9:8] map[9:8] scap[25] chip selection mcsn[1:0] scap[31:26] 2 2. to access the dram, sc[31:26] must be set to 0. otherwise, the dram controller will not respond to an scbus transaction. all zeros for dram access activate dram access virtual address physical address 0x b000 0000 0x 1000 0000 31 30 29 28 27 22 21 20 19 18 17 16 r pc mrs ref r cl r rcd 15 12 11 10 8 7 6 4 3 2 1 0 rc r ras r dal r rp3 dpl2
6-6 dram controller and memory bus r reserved 31 [27:22] [19:18] 11, 7 [3:2] these bits are not used. they should be cleared to 0. pc precharge command 30 this bit enables the manual precharge command. if the cpu sets the bit to 1, the dram controller generates one precharge command cycle for both banks. the cpu sets the bit at power up. initialization clears the bit automatically. mrs mode register set 29 if the cpu sets the bit to 1, the subsequent store word operation to the dram area generates a mode register set command. the row address bits in the sc address bus (scap[22:11]) select the addressed location during this type of operation. scap[31:23] and scap[10:0], which are the mode bits, must be set to 0. the cpu clears the mrs bit when the word operation has been completed. ref refresh cycle 28 this bit enables the manual refresh cycle request (ref). if the cpu sets it to 1, one refresh cycle is generated for both memory banks. this bit is cleared automatically when the refresh cycle has been completed. you can also generate ref using the refresh counter, as described in dram refresh on page 6-12 . cl cas latency [21:20] you can set cas latency by programming the bits in this ?eld. you should select one of the following settings: although you can de?ne all dram timing parameters independently, cas latency de?nes the relationship between other timing parameters. table 6.3 on page 6-10 shows the relationships between cas latency, dram frequency, and other con?guration settings. bit 21 bit 20 cache latency modes 01 1 10 2 11 3
dram controller con?guration register 6-7 bits [6:4] in the dram mode register also select the cycle modes. you must set or clear the bits in both registers, as described in cl cas latency [6:4] on page 6-11 , to select the required mode. rcd active ras to read/write command period cycles [17:16] you can program the bits in this ?eld to select the number of active clock cycles for a read or write operation. you can select one of the following settings: rc refresh to refresh/active command period cycles [15:12] this ?eld allows you to select the number of active read/write cycles between refresh cycles. you can program these bits as follows: bit 17 bit 16 active clock cycles 01 1 10 2 11 3 bit 15 bit 14 bit 13 bit 12 active read/ write cycles 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 101010
6-8 dram controller and memory bus ras active to precharge command period [10:8] this ?eld allows you to select the number of clock cycles that ras should stay active until the memory has been precharged. you can program the bits as follows: dal data in to active/refresh command period [6:4] this ?eld allows you to select the number of active clock cycles between the time data input is valid until the refresh command is asserted. you can set the ?eld as follows: rp3 precharge to active command period 1 this bit allows you to select the number of active clock cycles in the period between precharge and an active read or write command. if you set the bit to 1, there are three clock cycles. if you clear the bit to 0, there are two clock cycles. dpl2 data in to precharge command period 0 this bit allows you to select the number of active clock cycles in the period between the input of valid data to the assertion of the precharge command. if you set the bit to 1, there are two clock cycles. if you clear the bit to 0, there is one clock cycle. the relationship between latency and frequency varies, depending on the dram speci?cation. table 6.3 shows an example of the timing parameters for three nec dramsupd4516821, upd4516421, and upd4516161 drams. for the fastest access time, you should use a bit 10 bit 9 bit 8 active ras cycles 01 1 3 10 0 4 10 1 5 11 0 6 11 1 7 bit 6 bit 5 bit 4 active dal cycles 0113 1004 1015
dram controller con?guration register 6-9 dram with a maximum clock frequency of 10 ns. refer to the nec users manual for further information.
6-10 dram controller and memory bus 6.5 dram mode register the LR4500 supports a number of programmable modes by means of the dram mode register. the modes you can program are: cache write through and write back cache write through mode allows all data that is updated in the cache to be updated at the same time in external memory. in cache write back mode, main memory is only updated when the cache line is reallocated or is written back using the write back instruction. this mode does not apply in the LR4500, since the burst length ?eld is set to 0. burst length de?nes the number of words to be output or input during read and write cycles. in the LR4500, the burst length ?eld is set to 0. wrap type speci?es the order in which burst data is addressed. this mode does not apply in the LR4500, since the burst length ?eld is set to 0. table 6.3 relationship between frequency and latency clock frequencies register bit settings (-10) 1 1. maximum clock frequency for the 10 ns version of the dram. (-12) 2 2. maximum clock frequency for the 12 ns version of the dram. (-13) 3 3. maximum clock frequency for the 13 ns version of the dram. cl rcd rc ras dal rp dpl 100 mhz 83 mhz 75 mhz 3 3 10 7 5 3 2 80mhz- - 33865 3 2 66mhz55mhz50mhz22753 2 1 33mhz27mhz25mhz1143 2(3) 4 4. nec recommends 2 clock cycles for dal when cl is set to 1. however, the LR4500 dram controller requires 3 clock cycles for dal. 1(2) 5 5. nec recommends 1 clock cycle for rp when cl is set to 1. however, the LR4500 dram controller requires 2 clock cycles for rp. 1
dram mode register 6-11 cas latency de?nes the number of clock cycles that must occur before data is available. auto precharge this mode is not used in the LR4500. figure 6.4 shows the format of the 12-bit dram mode register. this register is programmed by a mode write command and is located in an sdram. figure 6.4 dram mode register format when you power up the dram, the boot program precharges the dram devices. you should refer to the documentation supplied with the dram for further information on precharging. after precharge, you must set the mrs bit in the dram controller con?guration register (see page 6-6 ). r reserved [11:10] [8:7] these bits are not used. they are set to 0. wb cache write through and write back 9 you can select cache write through mode by setting this bit to 1. setting the bit to 0 selects write back mode. however, there is no signi?cance to write through and write back modes in LR4500 transactions, since the burst length is one word. cl cas latency [6:4] you can select among one-, two-, and three-cycle modes by programming bits [6:4]. you should select one of the following settings. all other settings are reserved. 11 1098 76 432 0 r wb r cl wt bl bit 6 bit 5 bit 4 cache latency modes 00 1 1 01 0 2 01 1 3
6-12 dram controller and memory bus bits [21:20] in the dram controller con?guration register also select the cycle modes. you must set or clear the bits in both registers, as described in cl cas latency [21:20] on page 6-6 , to select the required mode. wt wrap type 3 sequential mode is compatible with scbus burst order- ing. since burst length is one word for the LR4500, wrap type is not used in the LR4500, so you should clear this bit to 0 to enable sequential accesses. setting the bit to 1 enables interleaved accesses. bl burst length [2:0] you can select single-cycle mode by clearing bits [2:0] of this register to 0b000. the scbus requests four double- words as a burst block. with a data bus width of 64 bits, the LR4500 supports the request with multiple cas accesses. 6.6 dram refresh the dram controller needs to refresh the 2048 rows in the synchronous dram every 32 milliseconds. the controller also needs to set up a 15,625 ns (15.625 m s) refresh interval. for example, if the maximum clock frequency is 66 mhz, the controller must issue a dram refresh command every 1,041 clock cycles. the dram controller has an 11-bit refresh interval timer that generates the refresh command. the refresh interval timer, shown in figure 6.5 , consists of one 11-bit register, referred to as the refresh register, which stores the refresh interval time; and one 11-bit binary countdown register, referred to as the refresh counter, which stores the refresh counter value, and is decremented by each system clock input. the refresh register address is shown below. virtual address physical address 0x b000 0004 0x 1000 0004
dram refresh 6-13 when the system is initialized, the dram controller writes the refresh interval time data into the refresh register . the same data is stored in the refresh counter as the refresh counter value. the dram controller reads the contents of both registers only during testing. figure 6.5 dram refresh interval timer after a cold reset, the counter stops counting. once the dram controller has written the value for the refresh interval time into the refresh register, the counter loads the same initial value and starts counting by decrementing the initial value by 1 at each clock input. when the counter has counted down to 1, the dram controller sets the ref bit in the LR4500 con?guration and cache control register ( page 3-5 ), requesting a refresh command. the initial value is then reloaded and the process starts again. note that the counter never counts down to 0. if a dram transaction is proceeding when the dram controller issues the refresh command, the status of the refresh command is pending, and a refresh command cycle is generated when the preceding transaction has been completed. only a cold reset can stop the refresh counter. the setting of the refresh register is derived from the dram clock cycle value, the required refresh interval (15,625 ns), and the cas latency (cl) setting. the cl setting determines the number of clock cycles required before data is available. table 6.4 lists refresh register programming values for four operating frequencies. you can calculate value a by dividing the refresh interval by the microprocessors clock cycle time. you can calculate the value programmed into the refresh register by subtracting the number of clock cycles required for the longest transaction, which is a burst read transaction (b), from the value a. in the ?rst example shown, the refresh register should be set to 1551 (0x61a). refresh register (write) 31 11 10 0 reserved (0) refresh interval time refresh counter (read) 31 11 10 0 reserved (0) refresh counter value
6-14 dram controller and memory bus ? 6.7 dram commands this section describes the dram commands used by the LR4500 dram controller. these commands are the chip select commands (mcsn[1:0]), row and column addresses strobes (rasn and casn), and the write enable command (mwen). the dram controller does not use the drams self-refresh entry command and burst stop command. in addition, for a no operation (nop), the dram controller deasserts the chip select outputs mcsn[1:0] and the other control signals. table 6.4 refresh register programming values clock frequency clock cycle time value (a) 1 1. value a is derived from the required refresh interval time (15,625 ns) divided by the clock cycle time (12.5 ns, and so forth). number of clock cycles required (b) 2 2. number of clock cycles required for a burst read transaction. refresh register programmed value 3 decimal (hex) 3. the refresh register programmed values is derived from value a minus value b. table 6.5 shows how the refresh register settings are arrived at. the example shown in the table is for the 80 mhz, 12.5 ns dram. cl setting 100 mhz 10 ns 1563 12 1551 (0x61a) 3 80 mhz 12.5 ns 1250 12 1238 (0x406) 3 66 mhz 15 ns 1041 10 1031 (0x407) 2 50 mhz 20 ns 781 8 773 (0x305) 1 table 6.5 refresh register setting for 80 mhz 12.5 ns dram register bits 31 30 29 28 27-11 10 9 8 7 6 5 43210 binary setting 0 0 0 0 x 1 0 0 1 1 0 10110 hex value 0 x 4 0 6 decimal value not used 1 2 3 8
initializing dram and programming the mode register 6-15 table 6.6 summarizes the settings of the mbus control signals and the dram commands they generate. scap[31:0] indicates the scbus address bit n associated with the memory bus address bit, map[31:0] ~ indicates an inverted signal ( ) indicates a dont care condition, but one in which the signals are output. for detailed information about dram commands, refer to the datasheet supplied with the sdram. 6.8 initializing dram and programming the mode register before the dram controller can access the dram for a normal read or write transaction, the boot program must initialize the dram through the dram controller. after power on, the dram controller goes through the following initialization process: table 6.6 summary of dram commands and mbus control signals command mcsn[1] mcsn[0] mrasn mcasn mwen map[11] map[10] map[9:0] no operation 1 1. mcsn[1:0] must both be kept high for no-operation conditions high high high high high (sca22) (sca21) (sca20:11) mode register set low low low low low sca22 sca21 sca[20:11] row active ~sca25 sca25 low high high sca22 sca21 sca[20:11] precharge 2 2. both banks are always precharged low low low high low sca22 high sca[20:11] write 3 3. when write or read commands are sent for a burst transaction, map[1:0] are incremented by the order of wrap around, starting from the requested address, for example, 01, 10, 11, then 00 ~sca25 sca25 high low low sca22 low sca24,23,[10:3] read 3 ~sca25 sca25 high low high sca22 low sca24,23,[10:3] cas before ras refresh low low low low high sca22 sca21 sca[20:11]
6-16 dram controller and memory bus precharges the dram programs the drams mode register refreshes the dram array twice the cpu can initiate this process by: 1. programming the dram con?guration register with the pc, mrs, and ref bits set to 1. 2. programming the dram mode register by initiating a store word operation to one of the addresses shown below: the address value is programmed to the sdram. write data is ignored. 3. programming the dram refresh register. once the dram controller has initialized the dram, it can initiate various types of dram accesses. figure 6.6 shows the timing requirements for the dram initialization sequence. table 6.7 lists the signals referenced in figure 6.6 and in subsequent timing diagrams. the signals are arranged in alphabetical order. cas latency (cl) physical address virtual address 1 0x0010 8000 0xa010 8000 2 0x0011 0000 0xa011 0000 3 0x0011 8000 0xa011 8000
initializing dram and programming the mode register 6-17 . table 6.7 timing signals signal name description other references aoereqp (internal) address output enable request dcinvsn d-cache invalidation strobe see minirisc cw4011 superscalar microprocessor core technical manual. doereqp (internal) data output enable request dramc state state of the dram controller drrdy data ready icinvsn i-cache invalidation strobe see minirisc cw4011 superscalar microprocessor core technical manual. ladsn lbus address strobe signals with an l pre?x are lbus signals. you will ?nd more detailed information about these signals in lbus interface on page 5-5 . la(o)p lbus address (output from LR4500) laoen lbus address enable lben lbus byte enable lclkp lbus clock ldp lbus data ldip lbus write data ldop lbus read data ldoen lbus data output enable lhldap lbus hold acknowledge lholdp lbus hold request lrd(o)n lbus data (output to LR4500) lrdyn lbus data ready lrdyoen lbus data ready output enable lslrdyin (internal) lbus sampled ready (sheet 1 of 2)
6-18 dram controller and memory bus map memory address signals with an m pre?x are mbus (memory bus) signals. you will ?nd more detailed information about these signals in mbus interface on page 5-2 . mcasn memory column address strobe mcsn memory chip select mdp memory data mdqmp memory data enable/mask mrasn memory row address strobe mwen memory write enable scap scbus address signals with an sc pre?x are cw4011 core scbus signals. you will ?nd more detailed information about these signals in the lsi logic technical manual minirisc cw4011 superscalar microproces- sor core. scben (sctben) scbus enable scbrdyn scbus ready scdp scbus data scdoen scbus data output enable schgtn scbus hold grant schrqn scbus hold request sclkp system clock sctbstn scbus burst transaction sctpwn scbus next transaction is in write page sctsen scbus transaction start enable sctssn scbus transaction start strobe sldoen sclc scbus data output enable bit names mrs mode register set page 6-6 pc precharge command page 6-6 ref refresh cycle table 6.7 timing signals (cont.) signal name description other references (sheet 2 of 2)
initializing dram and programming the mode register 6-19 figure 6.6 timing requirements for dram initialization sequence sclkp sctssn scapen scbrdyn scbrdyn mcsn[1:0] mrasn mcasn mwen map[11] map[10] (dramc state) (pc bit) (ref bit) refresh command mode register write command precharge command 3rd wr 2nd wr 1st wr idle pc pr3 idle mrw idle cbr idle cbr idle idle idle idle idle idle idle idle idle tpr 2clk trc (mrs bit) notes: 1st wr is the write to the dram con?guration register. 2nd wr is the write to the dram mode register. 3rd wr is the write to the dram refresh register. tpr = 3, trc = 10.
6-20 dram controller and memory bus 6.9 dram transactions once the dram controller has initialized the dram, it can initiate various types of dram accesses. this section shows the timing require- ments for three typical dram accesses: figure 6.7 shows the timing for a single burst read transaction. figure 6.8 ( page 6-22 ) shows the timing for two continuous write transactions. figure 6.9 ( page 6-23 ) shows the timing for a burst write transaction. in all cases, the dram is an 80 mhz, 10 ns device. other timing param- eters for this device are as follows: cas latency (cl) = 3. (refer to page 6-6 for further information about cl.) active ras to read/write command period cycles (rcd) = 3. (refer to page 6-7 for further information about rcd.) refresh to refresh/active command period cycles (rc) = 8. (refer to page 6-7 for further information about rc.) active to precharge command period (ras) = 6. (refer to page 6-8 for further information about ras.) precharge to active command period (rp) = 3. (refer to page 6-8 for further information about rp.) data in to precharge command period (dpl) = 2. (refer to page 6-8 for further information about dpl.) data in to active/refresh command period (dal) = 5. (refer to page 6-8 for further information about dal.)
dram transactions 6-21 figure 6.7 single burst read transaction sclkp scap, scben scdp drrdyn scaoen dramc state mcsn mrasn mcasn mwen map[11] map[10] map[9:0] idle ra rcd3 rcd2 rwc1 rwc2 rwc3 mdqmp mdp rwc4 pw3 tcl pw pc pr3 (ra) idle sctbstn t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 a11 a12 a13 a14 d13 d14 a11[22] a11[21] d11 d12 d13 d14 trcd tras trp a21[24,23,10:3] a11[20:11] a11 a12 a13 a14 d11 d12
6-22 dram controller and memory bus figure 6.8 two continuous single write transactions t18 sclkp scap, scben scdp drrdyn scaoen dramc state mcsn mrasn mcasn mwen map[11] map[10] map[9:0] idle ra rcd3 rcd2 rwc1 pw pw mdqmp mdp pc pr3 idle ra rcd3 rcd2 rwc1 pw pw pc pr3 idle sctpwn t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t19 a1 a2 a3 d1 d2 d3 a1[22] a2[22] a1[21] a2[21] a1[20:11] a2[20:11] d1 d2 tdal tdpl tras trcd trp tdal tdpl tras trcd a1[24,23,10:3] a2[24,23,10:3]
dram transactions 6-23 figure 6.9 burst write transaction sclkp scap, scben scdp drrdyn scaoen dramc state mcsn mrasn mcasn mwen map[11] map[10] map[9:0] idle ra rcd3 rcd2 rwc1 rwc2 rwc3 mdqmp mdp rwc4 pw pc pr3 idle (ra) sctbstn trp t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 a1 a2 a3 a4 d1 d2 d3 d4 a1[22] a1[21] a1[20:11] a1 a2 a3 a4 d1 d2 d3 d4 trcd tras tdpl tdal a1[24,23,10:3]
6-24 dram controller and memory bus
7-1 chapter 7 scbus and local i/o bus converter module this chapter discusses the lbus, and describes how the LR4500 microprocessor reference device interacts with the lbus through the sclc module. the chapter contains the following sections: lbus features , o n page 7-1 . LR4500 as master on the lbus , o n page 7-2 . LR4500 as slave on the lbus , o n page 7-5 . scbus timeout watchdog timer , o n page 7-8 . external vectored interrupt (evint) support , o n page 7-9 . 7.1 lbus features the lbus is similar to the vlbus or 486 bus, which has a demultiplexed 32-bit address bus and a 32-bit data bus. lbus interface on page 5-5 provides a list of lbus signals. there are certain differences between the lbus and the vlbus, as shown below: feature lbus vlbus i/o space no yes interrupt acknowledge cycle no yes support for single transactions yes yes support for burst transactions no yes hold/hlda bus arbitration yes yes bus retry input yes yes uses lbus clock, lclkp yes yes
7-2 scbus and local i/o bus converter module the lbus is synchronized by the lbus clock, lclkp, which is derived from the cw4011 system clock, sclkp. the LR4500 outputs the lclkp to the lbus. the LR4500 can function as the lbus master or the lbus slave. if the LR4500 is master, it starts an lbus transaction while lhldap is deasserted. if an lbus device wants to control the lbus and initiate a bus transaction, it must ?rst take ownership of the bus by issuing a bus hold request (by asserting lholdp) to the LR4500. the LR4500 returns a bus hold acknowledge signal (by asserting lhldap) to the lbus device, granting bus ownership. when this occurs, the lbus device may initiate lbus transactions. the lbus master starts a transaction on the lbus by asserting the address strobe, (ladsn). at this time, the master must also drive valid information on the address bus and the byte enable lines. the lbus master uses lrdn signal to control the direction of the data transfer. the master must present the appropriate level on this signal at the same time it asserts strobe signal ladsn. during a write transaction, the master must also drive valid data on the data bus. when the transaction has been successfully completed, the selected slave device asserts lrdyn, indicating that the lbus is ready for another transaction. the master must continue to drive all signals until it samples lrdyn. if the transaction is a read transaction, the slave device must place valid data on the bus before it asserts lrdyn. 7.2 LR4500 as master on the lbus the LR4500 is the master of the lbus when the cw4011 accesses an address in the lbus area located in the physical address range 0x1100 0000 through 0xffff ffff. the lbus device must assert a data ready or bus retry signal and input it to the LR4500 within 256 sclkp cycles. otherwise, the scbus watchdog timer terminates the scbus transaction by asserting a bus error signal. figure 7.1 shows the timing requirements for an lbus read transaction generated by the cw4011 core.
LR4500 as master on the lbus 7-3 figure 7.1 timing requirements for an scbus-to-lbus read transaction sclkp scap, scben scdp sldoen sctssn scdoen scbrdyn, scb32n sl0 sl0 sl1 sl2 sl2 sl3 sl3 sl3 sl3 sl3 sl0 sl1 sl3 sl3 sl3 sl4 sl0 sl-state sctsen lclkp adsreqp ladsn aoereqp laoen lap, lben lrdn lrdyn lslrdyin ldp doereqp ldoen t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16
7-4 scbus and local i/o bus converter module figure 7.2 timing requirements for an scbus-to-lbus write transaction sclkp scap, scben sldoen sctssn scdoen scbrdyn, scb32n scdp sl0 sl0 sl1 sl2 sl2 sl3 sl3 sl3 sl3 sl3 sl0 sl1 sl3 sl3 sl3 sl4 sl0 sl-state sctsen lclkp adsreqp ladsn aoereqp laoen lap, lben lrdn lrdyn lslrdyin ldp doereqp ldoen t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16
LR4500 as slave on the lbus 7-5 in the examples shown in figures 7.1 and 7.2 , the cw4011 initiates a scbus transaction at t1. the sclc module, which is part of the LR4500, checks the phase lclkp clock. at t4 and t5, the sclc asserts address strobe, ladsn. during a write transaction, the sclc must output data on the lbus on the rising edge of lclkp. the lbus transaction starts at t4. at t12, the sclc samples the lrdyn signal on the rising edge of lclkp. the sclc asserts the scbus data ready signal, scbrdyn, at t13. at the same time it asserts the bus sizing request signal, scb32n. during a read transaction, the sclc samples data on the lbus when it samples lrdyn. if the transaction is a write transaction, the cw4011 places data on the scbus at t13. 7.3 LR4500 as slave on the lbus LR4500 functions as a slave on the lbus when an lbus device, such as a sonic ethernet controller, initiates a bus transaction. the lbus device accesses the system dram through the dram controller, which is part of the LR4500 and the LR4500 acts as a slave memory controller. the address being accessed must fall in the range 0x 0000 0000 through 0x 03ff ffff. the LR4500 does not assert the data ready signal for the address range 0x 0400 0000 through 0x ffff ffff, since the transaction is treated as a read/write transaction between an lbus master and an lbus slave. figure 7.3 shows the timing requirements for an lbus-to-scbus read transaction. figure 7.4 shows the timing requirements for an lbus-to-scbus write transaction. at t1, the LR4500 samples lholdp on the rising edge of lclkp. at t2, the sclc module, which is part of the LR4500, asserts scbus hold request, schrqn. the cw4011 asserts the scbus hold grant signal, schgtn, at t4. at t7, the sclc module asserts the lbus hold acknowledge signal, lhldap, on the rising edge of lclkp. while lhldap is asserted, the sclc module asserts lrdyoen to drive lrdyn. at t9 or later, the lbus master starts an lbus transaction. the sclc samples ladsn on the rising edge of lclkp. if the signal is asserted, the sclc module knows the lbus master has initiated an lbus transaction. at t12, the sclc module decodes sampled address inputs and starts an scbus transaction if the address is in the dram area. the dram controller asserts the data ready signal, drrdyn, when a transaction is completed. at t17 and t18, the sclc module asserts lrdyn and the lbus transaction is completed.
7-6 scbus and local i/o bus converter module figure 7.3 timing requirements for lbus-to-scbus read transaction ls1 ls1 ls1 ls2 ls3 ls3 ls3 ls3 ls3 ls3 ls4 ls5 ls5 ls0 ls6 ls7 ls7 ls3 ls3 ls3 ls3 ls0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 schrqn schgtn dcinvsn icinvsn sclkp lclkp lholdp lhldap ladsn lrdyn lrdyoen lap, lben lrdn ldp ldop ldoen scap, scben scdp (read) sltssn drrdyn slaoen sldoen, slwrn
LR4500 as slave on the lbus 7-7 figure 7.4 timing requirements for lbus-to-scbus write transaction ls1 ls1 ls1 ls2 ls3 ls3 ls3 ls3 ls3 ls3 ls4 ls5 ls5 ls0 ls6 ls7 ls7 ls3 ls3 ls3 ls3 ls0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 schrqn schgtn dcinvsn icinvsn sclkp lclkp lholdp lhldap ladsn lrdyn lrdyoen lap, lben lrdn ldp ldip (write) ldoen scap, scben scdp sltssn drrdyn slaoen sldoen, slwrn
7-8 scbus and local i/o bus converter module 7.4 scbus timeout watchdog timer the sclc module in the LR4500 has a watchdog timer that it uses to time out scbus transactions. the timer monitors the number of clock cycles for each scbus transaction generated by the cw4011. it does not care about scbus transactions to sclc internal registers, or scbus transactions generated by the sclc module, since these transactions will never result in a timeout. when the cw4011 initiates an scbus transaction, the transaction must be completed within 256 sclkp clock cycles, timed from the cycle in which sctssn is asserted until the cycle in which scbrdyn or scbrtyn is asserted. if the transaction takes longer than 256 clock cycles, the timer terminates the transaction by asserting scberrn, which causes a bus error exception. the LR4500 has two registers that control scbus timeout errors. as shown in figure 7.5 , they are the error status register and the error address register. the status register stores bus error detect enable (bede) and bus error detected (berr) bits. the scbus watchdog timer starts when the bede bit is set. if a timeout error occurs, the timer sets the berr bit. during the time that berr is set, the address register stores the scbus transactions address and further bus error detection is inhibited. the sclc can clear the bit by writing a 1 to it. a cold reset clears both bits. figure 7.5 scbus error address and error status register bit format 31 31 0 0 1 berr reserved(0) error address [31:0] bede bede: bus error detect enable(1) berr: bus error was detected error address register error status register 2
external vectored interrupt (evint) support 7-9 the physical and virtual addresses for the registers are as follows: the sections scbus error address register and scbus error status register on page 3-10 provide further information about these registers. 7.5 external vectored interrupt (evint) support the LR4500 has a special interrupt exception input feature called external vectored interrupt. the sclc module provides test support for this feature with the exvi control register shown in figure 7.6 . figure 7.6 external vectored interrupt register bit format the physical and virtual addresses for the register are as follows: the section external vectored interrupt register on page 3-11 provides further information about these registers. when the LR4500 reads an exception vector address from exvap[31:2], it writes the address to the program counter. the evia[31:2] bits in the exvi register are connected to the exvap[31:2] bus to provide the vector address. when the LR4500 accepts an evint exception, it clears the evia bits to zero indicating that the timing was correct when the cw4011 sampled exvap[31:2]. register physical address virtual address scbus error address 0x1010 0000 0x b010 0000 scbus error status 0x1010 0004 0x b010 0004 31 0 1 sevi evia[31:2] hevi hevi: hardware external vectored interrupt sevi: software external vectored interrupt 2 register physical address virtual address external vectored interrupt 0x1010 0008 0x b010 0008
7-10 scbus and local i/o bus converter module if software sets the sevi bit in the exvi register, the evint input of LR4500 is asserted and causes an exception. external vectored interrupts are enabled in the ccc register, and interrupts are enabled in the status register. the software must write the extended address to the evia bit at the same time that it sets the sevi bit. the nonmaskable interrupt input to LR4500, nmi, can be used to cause an external vectored interrupt, evint. this bit selects the function of the nmi/evint pin. if the bit is cleared to 0, the pin generates a nonmaskable interrupt (nmi). if the bit is set to 1, the pin generates an external vectored interrupt (evint). the address is still supplied by the evia bits. if hevi is cleared to 0, the falling edge of nmi causes an nmi exception. if hevi is set to 1, the falling edge of nmi causes an evint exception provided that the interrupt enable bit the status register is set. a cold reset clears all bits of the exvi register. the evia[31:2] bits are cleared when the cw4011 reads them. evia[31:2] must be programmed again if they are to be used again.
8-1 chapter 8 cache con?guration and maintenance this section describes the LR4500 microprocessor i-cache and d-cache con?gurations, and explains how to maintain the caches after power is turned on. 8.1 cache con?guration LR4500 takes advantage of the largest i-cache and d-cache available. as described in section 3.3.1, ccc register, on page 3-5 , you can use the ccc register in cp0 to program certain features of the caches. this allows you to evaluate the performance of different cache con?gurations and select the one most appropriate for your application. you can con?gure the i-cache and d-cache independently of each other. you can program the ccc register to implement the following features: select the cache operating size. smaller cache con?gurations need wider tag bits. the LR4500 uses the maximum number of words for the maximum con?guration and the widest tag bits for the minimum con?guration. to set the size, you program bits is[1:0] for the i-cache, and ds[1:0] for the d-cache, as shown in table 8.1 .
8-2 cache con?guration and maintenance table 8.1 cache size and accessing select between direct-mapped and two-way set-associative caching. to do this you program bits ie[1:0] for the i-cache and de[1:0] for the d-cache, as shown in table 8.1 . ie1 and ie0 enable i-cache set- 1 and set-0, respectively, and de1 and de0 enable d-cache set-1 and set-0, respectively. in the example shown in table 8.1 , set-0 is enabled for both the i-cache and the d-cache when you require direct mapping, and set-1 is disabled for both caches. when you select two-way set-associative caching, both sets are enabled for both caches. note that when you select two-way set-associative caching, total cache capacity is doubled, since you are using both cache sets. con?gure the d-cache as scratchpad ram. prior to con?guring a sets associativity as scratchpad ram, you must use cache isolation and tag test modes to program the corre- sponding tag memory to contain the desired physical addresses. when using isolate cache mode, stores to cache are not propagated to external memory. to initiate isolate cache and test tags mode, you must set bits isc and tag in the ccc register, as described in section 3.3.1, ccc register, on page 3-5 . cache bit settings con?guration ie1 or de1 ie0 or de0 is[1:0] or ds[1:0] 00xx 1 1. the setting of these bits does not matter. no cache 0 1 0 0 1 kbyte direct mapped 0 1 0 1 2 kbyte direct mapped 0 1 1 0 4 kbyte direct mapped 0 1 1 1 8 kbyte direct mapped 1 1 0 0 2 kbyte two-way set-associative 1 1 0 1 4 kbyte two-way set-associative 1 1 1 0 8 kbyte two-way set-associative 1 1 1 1 16 kbyte two-way set-associative
cache con?guration 8-3 once this process is complete, you can con?gure the d-cache as scratchpad ram by programming bits de0 and sr0 to con?gure d-cache set-0, and de1 and sr1 to con?gure d-cache set-1, as shown in table 8.2 . con?gure the i-cache as instruction ram. prior to con?guring set-1 as instruction ram, you must use cache isolation and tag test modes to program the tag memory to contain the desired physical addresses. in addition, you must program the corresponding data ?elds to contain the instruction code which is to remain resident in the cache. to initiate isolate cache and test tags mode, you must set bits isc and tag in the ccc register. once this process is complete, you can con?gure the i-cache as instruction ram by programming bits ie1 and ir1 to con?gure i-cache set-1, as shown in table 8.3 . table 8.2 d-cache scratchpad ram con?guration cache bit settings con?guration de0 or de1 sr0 or sr1 0x 1 1. the setting of these bits does not matter. disabled 1 0 cache memory 1 1 data scratchpad ram table 8.3 i-cache instruction ram con?guration i-cache set-1 bit settings con?guration ie1 ir1 0x 1 1. the setting of this bit does not matter. disabled 1 0 cache memory 1 1 instruction ram
8-4 cache con?guration and maintenance 8.2 cache maintenance when power is turned on to the LR4500, valid bits in the tag memories have random values. before you program the ccc register to select a cache con?guration to enable caches, you must make sure that cache tag valid bits are cleared. cw4011 core has the following instructions that you can use to ?ush the caches: flushid ?ushes the i-cache and the d-cache flushi ?ushes the i-cache flushd ?ushes the d-cache these instructions do not have any operand. to invalidate i-cache and d-cache during reset initialization, use flushid. each ?ush instruction causes stall cycles for 256 clock cycles, regardless of cache size. you must execute the instructions from the kseg1 uncached and unmapped area.
9-1 chapter 9 iceport this chapter describes the cw4011 iceport building block and is divided into the following sections: section 9.1, overview page 9-1 section 9.2, iceport features page 9-2 section 9.3, iceport functional blocks page 9-3 section 9.4, iceport signals page 9-5 section 9.5, iceport registers page 9-9 section 9.6, iceport operations page 9-14 section 9.7, iceport pin buffers and drivers page 9-22 9.1 overview the iceport is a full-duplex serial uart (universal asynchronous receive and transmit) port available from lsi logic. it is an integral part of the LR4500 microprocessor reference device. you can use the iceport to download core application software and as a cw4011 debugging tool. the iceport works with the icecontroller at baud rates typically up to 1 mbaud/s 1 , providing 800 kbits of data per second. figure 9.1 shows a block diagram of a cw4011 system with the iceport installed. in the LR4500 con?guration, the iceport is integrated with the sclc and sdramc modules on the scbus. 1. actual baud rate depends on software, rom access times, and the cpu clock.
9-2 iceport figure 9.1 cw4011 design with iceport 9.2 iceport features the iceport has the following features: full-duplex operation. requires clock support at 16 times the transfer bit rate to de?ne receiving (rx) and transmitting (tx) rates. this clock is common for rx and tx, and may be either an external clock or one generated internally from the system clock. rx ready signal to indicate that a byte of data has been received and is in the data byte input buffer. separate status and data registers for rx and tx. the rx status register contains one bit that indicates received data is in the iceport, and one bit that indicates an overrun in the rx input buffer. the tx status register contains one bit that indicates the iceport is ready to transmit data. serial-receive and clock input do not require an active signal when the iceport is unused. during reset, the tx uart port defaults to an idle state and transmits an idle signal. cw4011 scbus rx input serial clock tx output rx interrupt scbus control signals sclc sdramc iceport core scbus control signals interrupt
iceport functional blocks 9-3 9.3 iceport functional blocks the cw4011 iceport design has been partitioned into three logical blocks: receive and transmit logic block that sends and receives the icetxp and icerxp signals. the generic interface logic block, common to most core designs, that implement a serialice iceport. the scbus interface logic block that connects the iceport with the rest of the cw4011 core by means of scbus signals. figure 9.2 shows how these blocks interact with each other and interface to other core logic and external logic. figure 9.2 iceport block diagram scbus icerxp icetxp iceclkp sc_icedip[7:0] sclkp sclkp irxrdyp operation cresetn wresetn scaop[31:0] scdoen sctssn sc_icerdyp sc_icedop[31:0] sc_icedoep scbus glue logic generic interface receive rx transmit tx iceport select read/write ready generation address control decode sc_iceintp iceport building block
9-4 iceport 9.3.1 receive and transmit interface logic the receive rx and transmit tx blocks make up the serial interface. the rx block receives the icerxp bit stream, and the tx block transmits the icetxp bit stream. both blocks receive the internal cpu clock (sclkp) and the external x 16 bit rate clock (iceclkp). both blocks synchronize timing between the iceclkp and sclkp timing domains. all interface signals between the rx and tx blocks and the generic interface are synchronized to sclkp, since the generic interface logic block runs on sclkp only. 9.3.2 generic interface logic the generic interface block connects the tx and rx blocks to a speci?c core bus interface, which is the scbus for the cw4011. the iceport directly outputs only the irxrdyp signal, which must be enabled in the rx setup register. when enabled, the irxrdyp signal indicates that rx data has been received. irxrdyp is tied to the processor interrupt signal (sc_iceintp) and may be used for interrupt generation as described in section 9.6.4.1, receive (rx) block. 9.3.3 scbus interface logic the scbus interface logic block connects the generic interface to the cw4011 scbus signals. the scbus is the main internal cw4011 bus that allows a bus master to exchange information with the cw4011 core. in scbus transactions, the iceport decodes the scbus address line and checks the transaction start signal (sctssn) to see if the current scbus transaction involves the iceport. if the current transaction involves the iceport, the scbus interface logic either places appropriate data on the data bus or writes data into an iceport internal register, depending on whether the current operation is a read or a write transaction. once either transaction is complete, the iceport asserts the acknowledge signal (sc_icerdyp) and the scbus interface logic begins to monitor scbus transactions again. please be aware that the iceport does not use the same scbus protocol as other cw4011 core components. the iceport uses only a certain subset of the scbus signals and combines several scbus acknowledge signals into a single iceport signal. see section 9.4.1, monitored scbus signals page 9-6 and section 9.4.2, other scbus signals page 9-7 for more information on iceport scbus interaction.
iceport signals 9-5 9.4 iceport signals this section describes the signals that comprise the bit-level interface of the iceport. the following paragraphs outline the conventions used in the signal descriptions: the signals are described in alphabetical order by mnemonic within each functional group. each signal de?nition contains the mnemonic and the full signal name. the mnemonics for signals that are active high, or for clock signals with a positive rising edge, end with a p; signals that are active low end with n. the term assert means to drive true or active; deassert means to drive false or inactive. input and output in the signal headings refer to i/os with respect to the iceport, not with the core. for example, sctssn is a core output, but it is considered an iceport input and therefore is labeled input. all input signals, except for icerxp and iceclkp, are read on the positive edge of sclkp and must therefore be generated synchronously with sclkp. all output signals (except icetxp) are also generated synchronously at the rising edge of the sclkp clock. the icetxp signal is synchronous to the rising edge of iceclkp, except during a reset where icetxp is asserted asynchronously to iceclkp. in normal serial send and receive operations through the iceport, iceclkp runs at 16 times the rate of serial bit transmission/receive. this allows iceclkp to de?ne the bit width for each uart serial bit. the iceport assumes that each serial bit for both receive and transmit is 16 x iceclkp, or 16 iceclkp cycles. table 9.1 summarizes the iceport signals. detailed descriptions follow the table. note that the scbus master can either be the sclc module or the cw4011 processor. external logic refers to logic not related to the cw4011 core, the sclc, or the iceport.
9-6 iceport 9.4.1 monitored scbus signals this section lists the scbus signals that the iceport monitors and outlines how the iceport uses these signals. for a more complete description of these signals, refer to section 5.2.1, scbus interface. cresetn cold reset input when the core asserts cresetn, it resets the iceport and all iceport registers. cresetn and wresetn are internally merged in the iceport. table 9.1 iceport signals group signal i/o source/target description monitored scbus signals cresetn input sclc cold reset wresetn input sclc warm reset scaop[31:2] input scbus master scbus address scdoen input scbus master data output enable (write low/read high) sctssn input scbus master transaction start signal other scbus signals sc_icedip[31:0] input scbus scbus input data bus sc_icedop[31:0] output scbus scbus output data bus sc_icedoep output scbus scbus output data valid sc_icerdyp output sclc iceport ready sc_iceintp output sclc iceport interrupt iceport scan and clocking signals sclkp input external logic system clock iceclkp input external logic ice bit rate clock x 16 icerxp input external logic rx serial bit receive icetxp output external logic tx serial bit transmit se input external logic scan test mode enable si input external logic scan test input so input external logic scan test output testmp output external logic scan test setup
iceport signals 9-7 scaop[31:0] scbus address bus input scaop[31:0] is the address bus. the iceport monitors this bus and sctssn for data read/write operations involving the iceport. when an scbus transaction involves the iceport, the iceport decodes scaop[31:0] to decide which internal register the transaction targets. scdoen scbus data output enable input the value of scdoen determines whether the present scbus transaction is a write or a read transaction. if it is a write, scdoen is driven low; if it is a read, scdoen is driven high. the iceport monitors scdoen so that it may perform the correct action for either a read or a write transaction. sctssn scbus transaction start signal input the core asserts sctssn for one clock cycle at the beginning of a transaction to announce that a new transaction has begun. asserting sctssn when address scaop[31:2] is valid initiates an iceport read/write operation. wresetn warm reset input when the core asserts wresetn, it resets the iceport and all iceport registers. cresetn and wresetn are internally merged in the iceport. 9.4.2 other scbus signals the signals described in this section enable iceport read and write operations and transfer data for these operations. sc_icedip[7:0] scbus input data bus input this is the scbus input data bus. for write operations to the iceport, data is transferred to the iceport through this bus. on the positive edge of the same sclkp that asserts sc_icerdyp, the core writes data into the iceport.
9-8 iceport sc_icedop[31:0] scbus output data bus output this is the scbus output data bus. for read operations from the iceport, the iceport will place data onto this bus. data on this bus is valid for one clock cycle and only when the sc_icedoep signal is asserted. sc_icedoep scbus output data valid output this signal is used to drive three-state buffers in the LR4500. asserting this signal indicates that the sc_icedop[31:0] bus is valid during the current cycle. sc_icedoep is asserted for read transactions only and lasts for only one sclkp cycle. sc_iceintp iceport interrupt output if this signal is enabled by the rxrxrdype bit in the rx setup register, the iceport asserts sc_iceintp once it receives a valid byte of off-chip data. sc_iceintp is input to the sclc module, which then generates an interrupt to the core in the sclc. sc_icerdyp iceport ready output asserting this signal high informs the core or the sclc module that the current transaction on the scbus has ?nished. sc_icerdyp encompasses both the scb32n and scbrdyn scbus control signals. 9.4.3 iceport scan and clocking i/o signals these signals are the scan and clocking i/o signals for the iceport. iceclkp ice serial bit clock rate x 16 input the iceport requires that this off-chip signal have a clock frequency 16 times greater than the serial transmit/receive rate. the iceport assumes each serial/transmit bit is 16 iceclkp cycles long. icerxp rx serial bit receive input this is an off-chip input that holds the uart serial input data stream. each received bit is 16 iceclkp cycles long.
iceport registers 9-9 icetxp tx serial bit transmit output this is an off-chip output that holds the uart serial output data stream. each transmitted bit is 16 iceclkp cycles long. sclkp system clock input sclkp is the global system clock input from the cw4011 core. se scan test mode enable input asserting se high enables the scan chain; deasserting se low disables the scan operation. the testmp signals must also be continuously asserted to enable the entire scan test. si scan test input input si is the scan chain data input signal. so scan test output output so is the scan chain data output signal. testmp scan test setup input when asserted high, this signal sets up the scan test, so that scan mode is possible in the sclkp clock domain. testmp signals must be continuously asserted to enable the scan test. the iceclkp signal is ignored while testmp is enabling the scan test mode. 9.5 iceport registers all iceport registers are memory-mapped as shown in table 9.2. the default iceport virtual base address is set to 0xb0ff 0000 (0x10ff 0000 physical address). users can customize the iceport address by altering the addresses in the hdl models. however, the last nibble (bits 0 to three) must be kept the same, since these four bits determine which iceport register to access. the addresses must also be both unmapped to prevent an installed mmu from remapping memory addresses and uncached to maintain data congruency. for these reasons, lsi logic suggests using unmapped and uncached memory space kseg1.
9-10 iceport all register read transactions return zeros for bits [31:8], and data for bits [7:0]. for read transactions, the register bits are mapped with scdip[31] to sc_icedop[31], and so on. for write transactions, the register bits are mapped with scdop[7] to sc_icedip[7], and so on. during write transactions, data on scdop[31:8] is ignored, write transactions to read- only registers are ignored, and read transactions from write-only registers return unde?ned data. all registers must be accessed using word accesses only, to avoid con?ict between big-endian and little-endian data structures, and to avoid partial update problems. table 9.2 iceport register addresses physical address virtual address access register 0x10ff0000 1 1. the physical address for the rx status register is the same as the physical address for the rx setup register. similarly, the virtual addresses are the same. the rx status register is a read register and the rx setup register is a write register. this means that when the addresses are accessed, the register accessed depends on the condition of the read/write signal. 0xb0ff0000 1 read rx status register 0x10ff0000 1 0xb0ff0000 1 write rx setup register 0x10ff0004 0xb0ff0004 read rx data register 0x10ff0008 0xb0ff0008 read tx status register 0x10ff000c 0xb0ff000c write tx data register
iceport registers 9-11 9.5.1 rx status register the read-only rx status register provides status information for iceport receive operations and indicates the state of the rx data register. figure 9.3 shows the rx status register. figure 9.3 rx status register res reserved bits [31:2] these bits are reserved for use by lsi logic and are read as zeros. rxoverrun rx overrun 1 this bit is set to one when an rx overrun error occurs. an rx overrun error occurs when a new rx byte is received, as indicated by rxrdy, before the previous rx byte has been read. for an overrun error, the new byte is not accepted and the pending byte in the rx data register is not lost. when the rxoverrun bit is set, it signals that at least one byte from the serial input stream of the new frame has been lost. rxoverrun is cleared when the rx status register is read. this ensures that if another overrun occurs between the rx status register read and the rx data register read that this overrun will set rxoverrun. rxoverrun clears to zero during an iceport reset. rxrdy rx byte ready 0 when the rx block receives a byte, this bit is set to 1. rxrdy clears to zero when the rx data register is read, and at reset. the irxrdyp (sc_iceintp) output signal, if enabled, re?ects the state of the rxrdy bit. 31 21 0 res rxoverrun rxrdy
9-12 iceport 9.5.2 rx setup register the write-only rx setup register enables and disables the sc_iceintp interrupt signal when the rxrdy bit in the rx status register is set. if software clears the rxrxrdype bit to zero, then the iceport interrupt signal sc_iceintp is disabled. this feature was added to allow software to disable the interrupt signal, irxrdyp (sc_iceintp). in the LR4500 reference device, the iceports interrupt irxrdyp (sc_iceintp) is tied to interrupt 4, which is a maskable interrupt. figure 9.4 shows the rx setup register, with bit ?eld descriptions following the ?gure. figure 9.4 rx setup register r reserved bits [31:1] these bits are reserved for lsi logic and any writes to these bits are ignored. rxrxrdype sc_iceintp (irxrdyp) enable 0 when this bit is set to one, the sc_iceintp signal re?ects the state of the rxrdy bit in the rx status register. when software clears rxrxrdype to zero, the sc_iceintp signal is continually deasserted. rxrxrdype clears to zero during an iceport reset. 9.5.3 rx data register the read-only rx data register, shown in figure 9.5 , holds received data in bits [7:0]. rxdata is valid only when the rxrdy bit in the rx status register is set. the rx data register is unde?ned after an iceport reset. 31 10 r rxrxrdype
iceport registers 9-13 figure 9.5 rx data register res reserved bits [31:8] these bits are reserved for lsi logic and are read as zeros. rxdata received bit stream [7:0], r this bit ?eld holds data received from the icerxp serial input signal. data held in rxdata is valid only when the rxrdy bit in the rx status register is set. rxdata is unde?ned after an iceport reset. 9.5.4 tx status register the tx status register, shown in figure 9.6 , provides status information for tx operations. figure 9.6 tx status register res reserved bits [31:1] these bits are reserved for lsi logic and are read as zeros. txrdy tx ready 0, r this bit is set to one when either the tx data register is ready for the next transmit byte, or after reset. txrdy remains set during and after the transmission of tx data. txrdy clears to zero during a write transaction to the tx data register. txrdy is set to one after an iceport reset. 31 8 7 0 res rxdata 31 10 res txrdy
9-14 iceport 9.5.5 tx data register the write-only tx data register, shown in figure 9.7 , holds the serial transmission data. figure 9.7 tx data register r reserved bits [31:8] these bits are reserved for lsi logic and any write transactions to these bits are ignored. txdata transmitted bit stream [7:0] when the txrdy bit in the tx status register is set, data that is to be transmitted through icetxp may be written to the txdata bits. write transactions to the txdata bits when txrdy is zero are ignored. 9.6 iceport operations this section describes the different iceport operations, and is divided into the following sections: section 9.6.1, scbus read/write transactions page 9-14 section 9.6.2, reset page 9-17 section 9.6.3, the serial bit stream page 9-18 section 9.6.4, iceport receive and transmit page 9-18 section 9.6.5, clock domains and properties page 9-21 9.6.1 scbus read/write transactions all read or write transactions to the iceport occur through the scbus. both transactions require two cycles once scbus arbitration is decided. for either transaction, the bus master must ?rst win arbitration for scbus control and decide to initiate a transaction. the bus master then places the target address for the transaction on scaop[31:0] and asserts sctssn for one cycle to indicate the start of a new transaction. the 31 8 7 0 r txdata
iceport operations 9-15 iceport constantly decodes scaop[31:0] and monitors sctssn for transactions that target the iceport. if the iceport is the target of a transaction, it checks the scdoen signal to determine whether this transaction is a read or a write transaction. for a read transaction, the iceport places data on the sc_icedop output bus, asserts both sc_icerdyp, and then asserts sc_icedoep at the next cycle. for a write transaction, the iceport latches the data on sc_icedip into the proper register on the next rising edge of the clock, and asserts sc_icerdyp at the following clock cycle. in order to ensure that information is not lost, the scbus master must hold the scaop[31:0], scdoen, and scdop[31:0] signals until the iceport asserts the sc_icerdyp acknowledge signal. for data transfer, the scdop[7:0] output bus connects to the iceport sc_icedip[31:0] input bus. the scdip[31:0] input bus connects to the iceport sc_icedop[31:0] output bus. the upper 32 bits of both scbus data buses, scdop[63:32] and scdip[63:32], are not used for iceport transactions. figure 9.8 shows the timing relationships for an iceport read transaction, and figure 9.9 shows the timing relationships for an iceport write transaction. in both examples, cresetn, wresetn, and testmp are assumed to be deasserted throughout the transaction, and these signals are not shown in the ?gures. all read/write transactions are synchronous to the rising edge of the sclkp. detailed cycle descriptions follow the ?gures.
9-16 iceport figure 9.8 read transaction figure 9.9 write transaction the following comments apply to cycles 1 through 4 in figure 9.8 and figure 9.9 . sclkp sctssn scaop[31:2] scdoen sc_icedop[31:0] sc_icerdyp cycle 2 cycle 3 cycle 1 sc_icedoep cycle 4 sclkp sctssn scaop[31:2] scdoen sc_icedip[7:0] sc_icerdyp cycle 2 cycle 3 cycle 1 cycle 4 sc_icedoep
iceport operations 9-17 cycle 1: the bus master wins arbitration of the scbus. cycle 2: the bus master asserts sctssn for one cycle to indicate the start of a new transaction. the bus master also places the target address on scaop[31:0] and asserts scdoen for a write transaction, or deasserts scdoen for a read transaction. for a write transaction, the bus master also drives scdop[31:0] with the data to be transferred. cycle 3: the iceport recognizes that it is the transaction target. for a read transaction, the iceport places the appropriate data on the sc_icedop[31:0] bus and asserts sc_icedoep. for a write transaction, the iceport writes sc_icedip[7:0] data into the appropriate register. the iceport then asserts sc_icerdyp to indicate that the transaction has ?nished. cycle 4: the iceport deasserts sc_icerdyp at the rising edge of sclkp. for a read transaction, the iceport also deasserts sc_icedoep and the scbus master must latch the data on the rising edge of sclkp at the start of this cycle. at the end of cycle 4, the iceport is ready to begin a new transaction. 9.6.2 reset an iceport system reset occurs when either cresetn or wresetn is asserted for at least one sclkp cycle. cresetn must be asserted when the system is powered up to set the iceport in a prede?ned state. since the reset signals are synchronous to sclkp, the iceport can be reset even if the iceclkp clock is not running. an iceport system reset performs the following functions: rxoverrun and rxrdy bits in the rx status register are cleared, indicating that the rx data register is unde?ned. the rxrxrdype bit in the rx setup register is cleared. this causes the irxrdyp (sc_iceintp) signal to be deasserted. the txrdy bit in the tx status register is set.
9-18 iceport 9.6.3 the serial bit stream the iceport receives data on icerxp and transmits data on icetxp in serial bit streams. in the receive (rx) block, the iceport receives data. when no data is being transferred, the transmit (tx) block holds icetxp idle high. figure 9.10 shows an interpretation of the serial bit stream on the data line. the data bytes are received in frames, with each frame consisting of three pieces: a start bit, always low a byte of data, transmitted at a true level from lsb (bit 0) to msb (bit 7) a stop bit, always high all bits in a frame are the 16 iceclkp cycles long. the data line remains high after the stop bit when the line goes idle, until the next start bit drives the line low. figure 9.10 serial bit stream 9.6.4 iceport receive and transmit there are two iceport serial interface blocks, speci?cally the receive (rx) and transmit (tx) blocks. the rx block receives the icerxp bit stream, and the tx block transmits the icetxp bit stream. both blocks receive the internal cpu clock (sclkp) and the external bit rate clock (iceclkp). both blocks synchronize timing between the iceclkp and sclkp timing domains. figure 9.11 shows a block diagram of the rx and tx blocks with i/o and clock signals. 0 1 2 3 4 5 6 7 data line bit positions frame idle state start data byte stop bit bit
iceport operations 9-19 figure 9.11 rx and tx blocks 9.6.4.1 receive (rx) block icerxp is the serial data input to the iceport. the rx block receives the icerxp signal and reads it on the rising edge of iceclkp, which can be used to generate both the transmit and receive data clocks, but usually two different clocks are implemented. this is not a problem, provided the difference between the two clock frequencies is below a certain limit, as outlined in section 9.6.5, clock domains and properties. the rx block is synchronized when icerxp has been high for nine bit times (144 iceclkp cycles) or more, which indicates that the data line is in an idle state. the rx block must be synchronized after power on, reset, serial cable connection, or any other event that would alter rx block synchronization. after synchronization, the rx block begins sampling icerxp on the rising edge of each iceclkp signal. when the rx block samples a low icerxp value, the rx block recognizes this as the start bit of a new data frame and prepares for the serial data stream. the width of each received bit is assumed to be 16 iceclkp cycles, even though the clock that generated the data for icerxp may be different from the iceclkp. the value of icerxp at the rising edge of the eighth iceclkp is assumed to be the value of the bit, and the bit is then received. if the start bit is high, the frame is ignored. in this case, the icerxp low value that indicated the start of the frame was accidental. figure 9.12 shows the serial bit clocking relative to iceclkp. icerxp icetxp iceclkp iceport sclkp transmit (tx) receive (rx) generic interface
9-20 iceport figure 9.12 received bit timing the rx block places in the rx data register the eight data bits received after the start bit. the ?rst data bit received after the start bit is the lsb (bit 0), and the eighth data bit received is the msb (bit 7). the eight data bits received between the start and stop bits are all true level values. a valid high stop bit received at the end of the frame sets the rxrdy bit in the rx status register. the irxrdyp (sc_iceintp) output re?ects the state of the rxrdy bit, if irxrdyp is enabled by the rxrxrdype bit in the rx setup register. irxrdyp can be used as an interrupt to ensure that the cpu reads the data received, thus avoiding overruns. if the stop bit is low, the frame is ignored. a received data byte is not placed in the rx data register until a valid stop bit is received. this data byte will be available through the next data byte (frame) receive, until the next valid stop bit refreshes the rx data register. in other words, a previously received data byte is present in the rx data register for at least nine bit cycles (144 iceclkp cycles) after a new start bit for a new frame is received. if a previously received byte has not been read when a new byte is ready for the rx data register, an overrun error occurs. when an overrun error occurs, the iceport sets the rxoverrun bit int he rx status register, and the new frame is discarded. if the iceport receives an invalid stop bit, the stop bit is not recorded by the iceport registers, but the frame is still discarded. the iceport will not accept a new start bit until the previous frame has been ?nished by a valid stop bit or a high value on icerxp. this ensures that the iceport will not indicate a runaway receive if icerxp is continuously either high or low. therefore, the iceport will not receive a frame after reset if icerxp is continuously either high or low. iceclkp 16 cycles icerxp start first second 16 cycles data bit data bit bit
iceport operations 9-21 when the rx block receives the stop bit correctly, a low value in the bit stream immediately following the stop bit will start the next frame. the start bit must be allowed to begin quickly, since iceclkp may be slower than the clock that generates the data for icerxp. in such a case, the next received frame may start on the next sample iceclkp. 9.6.4.2 transmit (tx) block the icetxp signal is the iceport serial data output and can carry new data every 16 iceclkp cycles. when there is no data for transmission, icetxp is held high in an idle state. during this idle state, the txrdy bit in the tx status register is set to one, which indicates that transmission may be initiated by placing data in the tx data register. after data is written to the tx data register, the iceport clears the txrdy bit to zero. start bit transmission begins on the rising edge of iceclkp and the ?rst data bit starts transmitting 16 iceclkp clock cycles later. every bit of the transmitted frame has a width of 16 iceclkp cycles. the tx data register lsb (bit 0) is transmitted just after the start bit; the msb (bit 7) is sent just before the stop bit. all data bits are transmitted true level, with zeros sent as low values and ones sent as high values. the iceport sets the txrdy bit in the tx status register when data bit 7 (the end of the byte) begins transmitting. as soon as txrdy is set, the next data byte to transmit can be written to the tx data register. writing to the tx data register while either data bit 7 or the stop bit is transmitting ensures that the icetxp signal will not be idle. if the next data byte is not written to the tx data register before the stop bit is transmitted, the tx block will idle for a number of iceclkp cycles, until new data is available in the tx data register. 9.6.5 clock domains and properties since data commonly moves between the iceclkp domain and the rx clock domain, these two clocks must have frequencies within certain limits. the difference between the iceclkp frequency and the icerxp clock frequency may be no more than 1%, with icerxp jitter margins 10% of the bit width. this jitter can originate from transmission cables or different timing in low-to-high and high-to-low transitions.
9-22 iceport the uart receiving the output from icetxp may, however, require less difference between the two frequencies, and this requirement must be observed. the iceclkp signal may be derived from sclkp by using a divider. this method frees a pin since iceclkp no longer requires an external pin. the operation of the iceport does not change in any way if iceclkp is derived from sclkp, but the frequency difference of 1% must be adhered to regardless of the clock rate. the iceport may also transfer data internally between the two clock domains (between iceport and the core). for these transactions, the iceclkp frequency can be at most one quarter of the sclkp frequency. no matter what the frequency difference between iceclkp and sclkp, the bus master must have enough time to read received data before new data arrives, otherwise, an overrun error will occur. 9.7 iceport pin buffers and drivers the choice of iceport external pin buffers and drivers will vary with each design. however, this section provides a few general recommendations for any design using an iceport. please note that the pin reserved for iceclkp may be conserved if the iceport clock is internally derived from sclkp, as described in section 9.6.5, clock domains and properties.. the buffer for input pin icerxp should b ea5v -compatible schmitt trigger with an internal pull-up resistor, since the incoming signal may be noisy and driven fro ma5v source. an internal pull-up resistor is recommended so that icerxp can be left unconnected if the iceport is unused. the driver for the icetxp output pin should be a 4 ma driver, with a reduced slew rate to avoid re?ections.
10-1 chapter 10 organization of clock and exception signals this section describes the organization of the LR4500 microprocessor clock circuitry that controls the LR4500s clock inputs and outputs, and LR4500 synchronization circuitry that handles exception inputs. 10.1 clock circuitry the pll circuit supplies the cw4011 core with the system clock, sclkp. figure 10.1 shows how the pll output is distributed to internal LR4500 modules, such as the dram controller and the sclc, as well as to the cw4011 core itself. the phase time of the sclkp inputs is the same for all internal modules. the LR4500 buffers sclkp and outputs it as mclkp, which monitors the internal clock, de?nes relative ac speci?cations for sclkp synchronized inputs and outputs, and may be used as the dram clock. the LR4500 generates the clock for the lbus by dividing sclkp either by 2 or by 4. sclkp is passed through a two-stage d-type ?ip-?op, as shown in figure 10.1 , and output to a 2:1 multiplexer, which is controlled by the lchalfn input. multiplexer input b generates the 1/2 clock while multiplexer input a generates the 1/4 clock. when lchalfn is high, it enables the input on pin b to be output on pin z of the multiplexer; when lchalfn is low, it enables the input on pin a to be output. the two-stage ?ip-?op is reset when lcresetn goes low. the lbus clock, lclkp, is buffered and used as an internal clock for the sclc. it is also output on the lbus to provide the clock for lbus devices. devices on the lbus sample all inputs on the rising edge of lclkp, and synchronize all outputs to the rising edge of lclkp.
10-2 organization of clock and exception signals table 10.1 summarizes the clock generation process. figure 10.2 shows the timing requirements for the cw4011 and lbus clocks. figure 10.1 LR4500 pll clock circuitry table 10.1 summary of LR4500 clocks clock name source frequency comments sclkp pin input sclkp dc to 100 mhz cw4011 clock mclkp sclkp same as sclkp frequency dram clock, sclkp monitor clock lclkp sclkp divided by 2, or sclkp divided by 4 1/2 or 1/4 of sclkp frequency lbus clock lcresetn dq qn cd internal lclkp internal sclkp (cw4011, dramc,sclc) (sclc) sclkp dq qn cd b a z s lchalfn sclkp -pin lclkp -pin lbus device clock input driver with pll output buffer internal clock buffer mclkp -pin sclkp monitor dram clock output buffer 2:1 multiplexer clock multiplexer input b generates the 1/2 clock, multiplexer input a generates the 1/4 clock when lchalfn is high, it enables the input on pin b to be output on pin z of the multiplexer, generating the 1/2 clock when lchalfn is low, it enables the input on pin a to be output on pin z of the multiplexer, generating the 1/4 clock
exception inputs 10-3 figure 10.2 timing requirements for the cw4011 and lbus clocks 10.2 exception inputs exception inputs to the LR4500 may be asynchronous. these inputs include: cold reset exception input, scresetn warm reset exception input, swresetn nonmaskable interrupt exception, snmin external interrupt exceptions, sextintn[5:0] the sclc module in the LR4500 has a synchronization circuit that synchronizes these inputs to the system clock, sclkp. as shown in figure 10.3 , the synchronization circuit consists of a series of d-type ?ip-?ops that are clocked on the rising edge of sclkp. the exception inputs reset the ?rst stage, flip-flop a. on the rising edge of sclkp, the q output from a is passed to the d-input of flip-flop b. the next sclkp input clocks this stage, and the q output from b is passed to the d-input of the ?nal stage, which outputs synchronous exception signals on the rising edge of the third sclkp. figure 10.4 shows the timing requirements for the synchronization circuit. sclkp sclkp lclkp lclkp lclkp lclkp mclkp (pin input) (internal signal) (pin output) (internal signal...1/2) (pin output...1/2) (internal signal...1/4) (pin output...1/4)
10-4 organization of clock and exception signals figure 10.3 exception inputs synchronization circuitry figure 10.4 timing requirements for synchronization circuit dq dq dq input sclkp synchronized output signals (cresetn wresetn nmin exintn[5:0]) asynchronous input signals (scresetn swresetn snmin sextintn[5:0]) flip-flop a flip-flop b flip-flop c sclkp asynchronous input flip-flop a (q) synchronized signal flip-flop b (q) case 1 asynchronous input width less than the sclkp cycle time case 2 asynchronous input width greater than the sclkp cycle time
11-1 chapter 11 speci?cations this chapter provides the speci?cations for the LR4500 microprocessor. the chapter contains the following sections: section 11.1, electrical characteristics page 11-1 section 11.2, packaging page 11-6 section 11.3, pinouts page 11-8 11.1 electrical characteristics this section de?nes the electrical characteristics of the LR4500 reference device. 11.1.1 absolute maximum ratings table 11.1 lists the absolute maximum ratings of the LR4500. table 11.1 absolute maximum ratings symbol parameter limits (referenced to vss) unit vdd dc supply - 0.3 to + 3.9 v (volts) vin input voltage - 1.0 to v dd + 0.3 v (volts) vin 5 v compatible input voltage - 1.0 to + 6.5 v (volts) iin dc input current 10 a(microamperes) 1 tstg storage temperature range - 40 to + 125 ?c (degrees centigrade) 1. except for power pins.
11-2 speci?cations 11.1.2 recommended operating conditions table 11.2 lists the recommended operating conditions for the LR4500. 11.1.3 input/output capacitance table 11.3 lists the capacitance of the LR4500s input and output signals. 11.1.4 dc characteristics table 11.4 lists the LR4500s dc characteristics. table 11.2 recommended operating conditions symbol parameter limits (referenced to vss) unit vdd dc supply, commercial + 3.15 to 3.45 volts tc case temperature 85 ?c degrees centigrade) table 11.3 input/output capacitance symbol parameter limits (referenced to vss) unit cin input capacitance 3.0 pf (picafarads) cout output capacitance 3.0 pf cio i/o buffer capacitance 3.0 pf
electrical characteristics 11-3 table 11.4 dc characteristics symbol parameter condition limits unit min. 1 typ. 2 max. 3 vil input voltage low not applicable - 0.5 0.8 v (volts) vih input voltage high 2.0 vdd + 0.3 v vol output voltage low 0.2 0.4 v voh output voltage high 2.4 vdd - 0.3 v iil input leakage current vdd = max. vin = vdd or vss - 10 1 + 10 a (microamperes) ioz 3-state output leakage current vdd = max. vin = vdd or vss - 10 1 + 10 a 1. minimum 2. typical 3. maximum
11-4 speci?cations 11.1.5 ac timing speci?cations table 11.5 lists the ac timing speci?cations for the LR4500. figure 11.1 ( page 11-5 ) shows timing relationships. the speci?cations are valid in the temperature range 0C85 ?c case; vdd 3.3 v, 5%. setup and hold times, which are relevant only for inputs to the LR4500, are referenced to the rising edge of the system clock (sclkp) or the lbus clock (lclkp). the valid maximum times are equivalent to hold time for the LR4500s outputs. they are not relevant for the inputs. they are referenced to the rising edge of sclkp or lclkp. for 3-state signals, valid maximum times include the period from high z to valid and valid to high z. (the z indicates the 3-state or off condition of the signal.) table 11.5 LR4500 ac timing speci?cations signal name reference clock input/ output (i/o) loading (pf) buffer type input timing output timing valid maximum (ns) setup (ns) hold (ns) map[11:0] mclkp o 50 b8rp 6.2 mdp[63:0] mclkp i/o 15 bd2c 1.0 0.5 6.8 mcsn[1:0] mclkp o 30 b6r 5.2 mrasn mclkp o 50 b8rp 5.5 mcasn mclkp o 50 b8rp 5.9 mwen mclkp o 50 b8rp 6.0 mdqmp[7:0] mclkp o 15 b2 5.0 lclkp sclkp o 50 b12 3.2 lap[31:2] lclkp i/o 50 bd4crf 10.0 0.0 9.7 ldp[31:0] lclkp i/o 50 bd4crf 3.5 0.5 12.7 lben[3:0] lclkp i/o 50 bd4crf 9.0 0.0 9.8 lrdn 1 lclkp i/o 50 bd4crf 9.0 0.0 8.3 ladsn 1 lclkp i/o 50 bd4crf 2.0 0.0 8.0 lrdyn 1 lclkp i/o 50 bd4crf 2.0 0.5 8.0 lrtyn 1 lclkp i ibuff 2.0 0.5
electrical characteristics 11-5 the following parameters are critical and you should check them carefully. 1. mbus outputs valid minimumdram requirement time is 1 ns. 2. lbus outputs valid minimumrelated data hold-time parameters for lbus devices. figure 11.1 ac timing for LR4500 inputs and outputs lholdp 1 lclkp i ibuff 3.5 0.0 lhldap 1 lclkp o 30 b2 6.0 scresetn 1, 2 sclkp i schmitcf 1.5 0.5 swresetn 1, 2 sclkp i ibuff 0.0 1.0 snmin 1, 2 sclkp i ibuff 0.0 1.0 sexintn[5:0] 1, 2 sclkp i ibuff 0.0 1.0 icerxp sclkp i schmitcf 0.5 1.0 icetxp sclkp i 50 b4 9.0 1. setup and hold times guaranteed by design. 2. these are asynchronous inputs that are synchronized in the LR4500. input setup and hold times specify the times these signals are sampled. table 11.5 (cont.) LR4500 ac timing speci?cations signal name reference clock input/ output (i/o) loading (pf) buffer type input timing output timing valid maximum (ns) setup (ns) hold (ns) valid hold delay reference clock (sclkp or lclkp) outputs reference clock (sclkp or lclkp) inputs outputs timing for ac inputs timing for ac outputs input hold input setup valid maximum
11-6 speci?cations 11.2 packaging this section provides packaging information for the LR4500 reference device. figure 11.2 shows the mechanical layout and dimensions, and the pin locations. figure 11.2 256 pqfpt mechanical drawing for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code un. md97.un-1
packaging 11-7 figure 11.2 (cont.)256 pqfpt mechanical drawing for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code un. md97.un-2
11-8 speci?cations 11.3 pinouts this section de?nes the LR4500 pinouts. figure 11.3 shows an outline of the device and identi?es the pins. table 11.6 lists the pinouts alphabetically. figure 11.3 256 pqfpt pinouts 12 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 64 245 256 253 252 251 250 249 248 247 246 244 243 242 241 240 239 238 237 236 235 234 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 193 233 180 192 188 187 186 185 184 183 182 181 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 135 134 133 132 131 129 76 65 68 69 70 71 72 73 74 75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 128 LR4500 mdqmp.1 mdp.12 mdp.13 mdp.14 mdp.15 vdd2 vss2 vdd vss mdp.16 mdp.17 mdp.18 mdp.19 mdp.20 mdp.21 mdp.22 mdp.23 mdqmp.2 vss mdp.24 mdp.25 vdd2 vss2 mdp.26 mdp.27 mdp.28 mdp.29 mdp.30 mdp.31 vss mdqmp.3 mdp.32 mdp.33 mdp.34 mdp.35 mdp.36 vdd2 vss2 vdd vss mdp.37 mdp.38 mdp.39 mdqmp.4 mdp.40 mdp.41 mdp.42 mdp.43 mdp.44 mdp.45 vss mdp.46 mdp.47 vdd2 vss2 mdqmp.5 mdp.48 mdp.49 vss mdp.58 mdp.51 mdp.54 mdp.55 vss mdqmp.6 vdd2 vss2 mdp.56 mdp.57 mdp.59 mdp.60 mdp.61 mdp.62 mdp.63 vdd vss mdqmp.7 map.11 map.10 map.9 vdd2 vss2 map.8 map.7 map.6 map.5 map.4 vss map.3 map.1 map.0 mclkp mwen mcsn.1 mcsn.0 mrasn vss2 vdd2 mcasn scanenbp vdd vss vss sexintn.5 sexintn.4 sexintn.3 sexintn.2 sexintn.1 sexintn.0 frcmn lben.0 vdd2 vss2 lben.1 paramoutp iceclkp testmp scancrop vss mdp.8 mdp.7 mdp.6 mdp.5 mdp.4 vss2 vdd2 mdp.3 mdp.2 vdd mdp.1 mdp.0 lben.3 lben.2 lholdp lap.2 lap.3 vss vss2 vdd2 lap.4 lap.5 lap.6 lap.7 lap.8 lap.9 lap.10 lap.11 lap.12 lap.13 vss lap.14 lap.15 lap.16 vss2 vdd2 lap.17 lap.18 lap.19 lap.20 lap.21 snmin vss vss vdd screse t lap.22 lap.23 lap.24 lap.25 lap.26 lap.27 lap.28 vss2 vdd2 lap.29 lap.30 lclkp ldp.30 ldp.22 ldp.29 ldp.27 ldp.26 ldp.25 vss2 vdd2 ldp.24 ldp.23 ldp.21 ldp.20 ldp.19 ldp.18 ldp.17 ldp.16 ldp.15 vss ldp.14 ldp.13 ldp.12 vdd2 ldp.11 ldp.10 ldp.9 ldp.8 ldp.7 ldp.6 ldp.5 ldp.4 ldp.3 ldp.2 ldp.1 lchalfn pllvss plllp2p pllagnd pllvdd pllrefp pllenp pllctop vss2 vdd2 lhldap pllctrn plltdp plltstp plliddtp vss vdd vss2 vdd2 ldp.0 lrdyn lrtyn lcresetn zstaten bendn vss2 ladsn map.2 2 mdp.10 3 mdp.11 1 mdp.9 63 vdd 62 mdp.50 66 mdp.52 67 mdp.53 130 icetxp 189 ldp.28 190 vdd 195 lap.31 194 ldp.31 255 mdqmp.0 254 vss 126 swresetn 127 icerxp 191 vss 136 lrdn
pinouts 11-9 table 11.6 LR4500 alphabetical pin list vdd2 72 vdd2 88 vdd2 106 vdd2 120 vdd2 138 vdd2 147 vdd2 168 vdd2 184 vdd2 199 vdd2 218 vdd2 234 vdd2 248 vss 11 vss 22 vss 33 vss 43 vss 54 vss 64 vss 70 vss 83 vss 95 vss 110 vss 111 vss 141 vss 173 vss 191 vss 210 vss 211 vss 223 vss 236 vss 245 vss 254 vss2 9 vss2 26 vss2 41 vss2 58 vss2 73 vss2 89 vss2 105 vss2 121 vss2 139 vss2 148 vss2 169 vss2 185 vss2 200 vss2 219 vss2 235 vss2 249 zstaten 131 signal pin signal pin bendn 129 frcmn 118 iceclkp/ scanrip 124 icerxp 127 icetxp 130 lap.2 238 lap.3 237 lap.4 233 lap.5 232 lap.6 231 lap.7 230 lap.8 229 lap.9 228 lap.10 227 lap.11 226 lap.12 225 lap.13 224 lap.14 222 lap.15 221 lap.16 220 lap.17 217 lap.18 216 lap.19 215 lap.20 214 lap.21 213 lap.22 207 lap.23 206 lap.24 205 lap.25 204 lap.26 203 lap.27 202 lap.28 201 lap.29 198 lap.30 197 lap.31 195 ladsn 133 lben.0 119 lben.1 122 lben.2 240 lben.3 241 lchalfn 156 lclkp 196 lcresetn 132 ldp.0 137 ldp.1 157 ldp.2 158 ldp.3 159 ldp.4 160 ldp.5 161 ldp.6 162 ldp.7 163 ldp.8 164 ldp.9 165 ldp.10 166 ldp.11 167 ldp.12 170 ldp.13 171 ldp.14 172 ldp.15 174 ldp.16 175 ldp.17 176 ldp.18 177 ldp.19 178 ldp.20 179 ldp.21 180 ldp.22 181 ldp.23 182 ldp.24 183 ldp.25 186 ldp.26 187 ldp.27 188 ldp.28 189 ldp.29 192 ldp.30 193 ldp.31 194 lhldap 146 lholdp 239 lrdn 136 lrdyn 135 lrtyn 134 map.0 99 map.1 98 map.2 97 map.3 96 map.4 94 map.5 93 map.6 92 map.7 91 map.8 90 map.9 87 map.10 86 map.11 85 mcasn 107 mclkp 100 mcsn.0 103 mcsn.1 102 mdp.0 242 mdp.1 243 mdp.2 246 mdp.3 247 mdp.4 250 mdp.5 251 mdp.6 252 mdp.7 253 mdp.8 256 mdp.9 1 mdp.10 2 mdp.11 3 mdp.12 4 mdp.13 5 mdp.14 6 mdp.15 7 mdp.16 13 mdp.17 14 mdp.18 15 mdp.19 16 mdp.20 17 mdp.21 18 mdp.22 19 mdp.23 20 mdp.24 23 mdp.25 24 mdp.26 27 mdp.27 28 mdp.28 29 mdp.29 30 mdp.30 31 mdp.31 32 mdp.32 35 mdp.33 36 mdp.34 37 mdp.35 38 mdp.36 39 mdp.37 44 mdp.38 45 mdp.39 46 mdp.40 48 mdp.41 49 mdp.42 50 mdp.43 51 mdp.44 52 mdp.45 53 mdp.46 55 mdp.47 56 mdp.48 60 mdp.49 61 mdp.50 62 mdp.51 65 mdp.52 66 mdp.53 67 mdp.54 68 mdp.55 69 mdp.56 74 mdp.57 75 mdp.58 76 mdp.59 77 mdp.60 78 mdp.61 79 mdp.62 80 mdp.63 81 mdqmp.0 255 mdqmp.1 12 mdqmp.2 21 mdqmp.3 34 mdqmp.4 47 mdqmp.5 59 mdqmp.6 71 mdqmp.7 84 mrasn 104 mwen 101 paramoutp123 pllagnd 153 pllctrn 145 pllctop 149 pllenp 150 plliddtp 142 plllp2p 154 pllrefp 151 plltdp 144 plltstp 143 pllvdd 152 pllvss 155 scancrop 128 scanenbp 108 scresetn 208 sexintn.0 117 sexintn.1 116 sexintn.2 115 sexintn.3 114 sexintn.4 113 sexintn.5 112 snmin 212 swresetn 126 testmp 125 vdd 10 vdd 42 vdd 63 vdd 82 vdd 109 vdd 140 vdd 190 vdd 209 vdd 244 vdd2 8 vdd2 25 vdd2 40 vdd2 57 signal pin signal pin signal pin 1. nc pins are not connected.
11-10 speci?cations
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u.s. distributors by state h. h. hamilton hallmark w. e. wyle electronics alabama huntsville h. h. tel: 205.837.8700 w. e. tel: 800.964.9953 alaska h. h. tel: 800.332.8638 arizona phoenix h. h. tel: 602.736.7000 w. e. tel: 800.528.4040 tucson h. h. tel: 520.742.0515 arkansas h. h. tel: 800.327.9989 california irvine h. h. tel: 714.789.4100 w. e. tel: 800.626.9953 los angeles h. h. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento h. h. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego h. h. tel: 619.571.7540 w. e. tel: 800.829.9953 san jose h. h. tel: 408.435.3500 santa clara w. e. tel: 800.866.9953 woodland hills h. h. tel: 818.594.0404 colorado denver h. h. tel: 303.790.1662 w. e. tel: 800.933.9953 connecticut chesire h. h. tel: 203.271.5700 wallingford w. e. tel: 800.605.9953 delaware north/south h. h. tel: 800.526.4812 tel: 800.638.5988 florida fort lauderdale h. h. tel: 305.484.5482 w. e. tel: 800.568.9953 orlando h. h. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg h. h. tel: 813.507.5000 georgia atlanta h. h. tel: 770.623.4400 w. e. tel: 800.876.9953 hawaii h. h. tel: 800.851.2282 idaho h. h. tel: 801.266.2022 illinois north/south h. h. tel: 847.797.7300 tel: 314.291.5350 chicago w. e. tel: 800.853.9953 indiana indianapolis h. h. tel: 317.575.3500 w. e. tel: 317.581.6152 iowa cedar rapids h. h. tel: 319.393.0033 kansas kansas city h. h. tel: 913.663.7900 kentucky central/northern/ western h. h. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana north/south h. h. tel: 800.231.0253 tel: 800.231.5575 maine h. h. tel: 800.272.9255 maryland baltimore h. h. tel: 410.720.3400 w. e. tel: 800.863.9953 massachusetts boston h. h. tel: 508.532.9808 w. e. tel: 800.444.9953 marlborough w. e. tel: 508.480.9900 michigan detroit h. h. tel: 313.416.5800 w. e. tel: 888.318.9953 grandville h. h. tel: 616.531.0345 minnesota minneapolis h. h. tel: 612.881.2600 w. e. tel: 800.860.9953 mississippi h. h. tel: 800.633.2918 missouri st. louis h. h. tel: 314.291.5350 montana h. h. tel: 800.526.1741 nebraska h. h. tel: 800.332.4375 nevada las vegas h. h. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire h. h. tel: 800.272.9255 new jersey north/south h. h. tel: 201.515.1641 tel: 609.222.6400 oradell w. e. tel: 201.261.3200 pine brook w. e. tel: 800.862.9953 new mexico albuquerque h. h. tel: 505.293.5119 new york long island h. h. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester h. h. tel: 716.475.9130 w. e. tel: 800.319.9953 syracuse h. h. tel: 315.453.4000 north carolina raleigh h. h. tel: 919.872.0712 w. e. tel: 800.560.9953 north dakota h. h. tel: 800.829.0116 ohio cleveland h. h. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton h. h. tel: 614.888.3313 w. e. tel: 800.763.9953 oklahoma tulsa h. h. tel: 918.459.6000 oregon portland h. h. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania pittsburgh h. h. tel: 412.281.4150 philadelphia h. h. tel: 800.526.4812 w. e. tel: 800.871.9953 rhode island h. h. 800.272.9255 south carolina h. h. tel: 919.872.0712 south dakota h. h. tel: 800.829.0116 tennessee east/west h. h. tel: 800.241.8182 tel: 800.633.2918 texas austin h. h. tel: 512.219.3700 w. e. tel: 800.365.9953 dallas h. h. tel: 214.553.4300 w. e. tel: 800.955.9953 el paso h. h. tel: 800.526.9238 houston h. h. tel: 713.781.6100 w. e. tel: 800.888.9953 rio grande valley h. h. tel: 210.412.2047 utah draper w. e. tel: 800.414.4144 salt lake city h. h. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont h. h. tel: 800.272.9255 virginia h. h. tel: 800.638.5988 washington seattle h. h. tel: 206.882.7000 w. e. tel: 800.248.9953 wisconsin milwaukee h. h. tel: 414.513.1500 w. e. tel: 800.867.9953 wyoming h. h. tel: 800.332.9326
sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california irvine tel: 714.553.5600 fax: 714.474.8101 san diego tel: 619.613.8300 fax: 619.613.8350 silicon valley sales of?ce tel: 408.433.8000 fax: 408.954.3353 design center tel: 408.433.8000 fax: 408.433.7695 colorado boulder tel: 303.447.3800 fax: 303.541.0641 florida boca raton tel: 561.989.3236 fax: 561.989.3237 illinois schaumburg tel: 847.995.1600 fax: 847.995.1622 kentucky bowling green tel: 502.793.0010 fax: 502.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey edison tel: 732.549.4500 fax: 732.549.4802 new york new york tel: 716.223.8820 fax: 716.223.8822 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 dallas tel: 972.509.0350 fax: 972.509.0349 washington issaquah tel: 425.837.1733 fax: 425.837.1734 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 toronto tel: 416.620.7400 fax: 416.620.5005 quebec montreal tel: 514.694.2417 fax: 514.694.2699 international australia reptechnic pty ltd new south wales tel: 612.9953.9844 fax: 612.9953.9683 denmark lsi logic development centre ballerup tel: 45.44.86.55.55 fax: 45.44.86.55.56 france lsi logic s.a. immeuble europa paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany lsi logic gmbh munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 hong kong avt industrial ltd hong kong tel: 852.2428.0008 fax: 852.2401.2105 india logicad india private ltd bangalore tel: 91.80.526.2500 fax: 91.80.338.6591 israel lsi logic ramat hasharon tel: 972.3.5.480480 fax: 972.3.5.403747 vlsi development centre netanya tel: 972.9.657190 fax: 972.9.657194 italy lsi logic s.p.a. milano tel: 39.39.687371 fax: 39.39.6057867 japan lsi logic k.k. tokyo tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea lsi logic corporation of korea ltd. seoul tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands lsi logic europe ltd eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore lsi logic pte ltd singapore tel: 65.334.9061 fax: 65.334.4749 spain lsi logic s.a. madrid tel: 34.1.556.07.09 fax: 34.1.556.75.65 sweden lsi logic ab stockholm tel: 46.8.444.15.00 fax: 46.8.750.66.47 switzerland lsi logic sulzer ag brugg/biel tel: 41.32.536363 fax: 41.32.536367 taiwan lsi logic asia-paci?c taipei tel: 886.2.2718.7828 fax: 886.2.2718.8869 jeilin technology corporation, ltd. taipei tel: 886.2.2248.4828 fax: 886.2.2242.4397 lumax international corporation, ltd taipei tel: 886.2.2788.3656 fax: 886.2.2788.3568 united kingdom lsi logic europe ltd bracknell tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers

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